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Searched refs:dml_dispcfg (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/
Ddml2_translation_helper.c1090 const struct dc_stream_state *stream, const struct dml_display_cfg_st *dml_dispcfg) in map_stream_to_dml_display_cfg() argument
1130 …const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_… in map_plane_to_dml_display_cfg() argument
1151 …gs(struct dml2_context *dml2, const struct dc_state *state, struct dml_display_cfg_st *dml_dispcfg) in apply_legacy_svp_drr_settings() argument
1157 dml_dispcfg->timing.DRRDisplay[0] = true; in apply_legacy_svp_drr_settings()
1160 for (i = 0; i < dml_dispcfg->num_timings; i++) { in apply_legacy_svp_drr_settings()
1162 dml_dispcfg->timing.DRRDisplay[i] = true; in apply_legacy_svp_drr_settings()
1265 …ay_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg) in map_dc_state_into_dml_display_cfg() argument
1280 dml_dispcfg->plane.GPUVMEnable = dml2->v20.dml_core_ctx.ip.gpuvm_enable; in map_dc_state_into_dml_display_cfg()
1281 dml_dispcfg->plane.GPUVMMaxPageTableLevels = dml2->v20.dml_core_ctx.ip.gpuvm_max_page_table_levels; in map_dc_state_into_dml_display_cfg()
1282 dml_dispcfg->plane.HostVMEnable = dml2->v20.dml_core_ctx.ip.hostvm_enable; in map_dc_state_into_dml_display_cfg()
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Ddml2_utils.c465 …d_stream_count(struct dml2_context *in_ctx, struct dml_display_cfg_st *dml_dispcfg, int *num_of_pl… in find_planes_per_stream_and_stream_count() argument
469 for (plane_index = 0; plane_index < dml_dispcfg->num_surfaces; plane_index++) { in find_planes_per_stream_and_stream_count()
473 …if (plane_index + 1 < dml_dispcfg->num_surfaces && dml_dispcfg->plane.BlendingAndTiming[plane_inde… in find_planes_per_stream_and_stream_count()
482 …y_det_buffer_allocation_policy(struct dml2_context *in_ctx, struct dml_display_cfg_st *dml_dispcfg) in dml2_apply_det_buffer_allocation_policy() argument
489 …num_of_streams = find_planes_per_stream_and_stream_count(in_ctx, dml_dispcfg, num_of_planes_per_st… in dml2_apply_det_buffer_allocation_policy()
491 for (plane_index = 0; plane_index < dml_dispcfg->num_surfaces; plane_index++) { in dml2_apply_det_buffer_allocation_policy()
494 dml_dispcfg->plane.DETSizeOverride[plane_index] = max_det_size / in_ctx->config.dcn_pipe_count; in dml2_apply_det_buffer_allocation_policy()
496 …dml_dispcfg->plane.DETSizeOverride[plane_index] = ((max_det_size / num_of_streams) / num_of_planes… in dml2_apply_det_buffer_allocation_policy()
501 if (dml_dispcfg->plane.DETSizeOverride[plane_index] % in_ctx->config.det_segment_size != 0) { in dml2_apply_det_buffer_allocation_policy()
502 …dml_dispcfg->plane.DETSizeOverride[plane_index] = dml_dispcfg->plane.DETSizeOverride[plane_index] … in dml2_apply_det_buffer_allocation_policy()
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Ddml2_translation_helper.h37 …y_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg);
Ddml2_utils.h131 …_det_buffer_allocation_policy(struct dml2_context *in_ctx, struct dml_display_cfg_st *dml_dispcfg);
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/
Ddml21_translation_helper.c952 struct dml2_display_cfg *dml_dispcfg = &dml_ctx->v21.display_config; in dml21_map_dc_state_into_dml_display_cfg() local
957 dml_dispcfg->gpuvm_enable = dml_ctx->config.gpuvm_enable; in dml21_map_dc_state_into_dml_display_cfg()
958 dml_dispcfg->gpuvm_max_page_table_levels = 4; in dml21_map_dc_state_into_dml_display_cfg()
959 dml_dispcfg->hostvm_enable = false; in dml21_map_dc_state_into_dml_display_cfg()
960 dml_dispcfg->minimize_det_reallocation = true; in dml21_map_dc_state_into_dml_display_cfg()
961 dml_dispcfg->overrides.enable_subvp_implicit_pmo = true; in dml21_map_dc_state_into_dml_display_cfg()
964 dml_dispcfg->overrides.hw.force_unbounded_requesting.enable = true; in dml21_map_dc_state_into_dml_display_cfg()
965 dml_dispcfg->overrides.hw.force_unbounded_requesting.value = false; in dml21_map_dc_state_into_dml_display_cfg()
972 disp_cfg_stream_location = dml_dispcfg->num_streams++; in dml21_map_dc_state_into_dml_display_cfg()
975 …populate_dml21_timing_config_from_stream_state(&dml_dispcfg->stream_descriptors[disp_cfg_stream_lo… in dml21_map_dc_state_into_dml_display_cfg()
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