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Searched refs:dml2_core_internal_soc_state_max (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
Ddml2_core_shared_types.h164 dml2_core_internal_soc_state_max enumerator
301 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max];
302 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
303 …double urg_bandwidth_available_min_latency[dml2_core_internal_soc_state_max]; // min between SDP a…
304 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM
305 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
306 …double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and…
307 …double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp b…
309 double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
310 …double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]…
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Ddml2_core_shared.c240 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max],
241 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],
242 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max], // min between SDP and DRAM
243 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],
244 double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max],
245 double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max],
253 double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],
572 double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],
573 double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],
574 double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max],
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Ddml2_core_utils.c184 case dml2_core_internal_soc_state_max: in dml2_core_utils_internal_soc_state_type_str()
Ddml2_core_dcn4_calcs.c38 case dml2_core_internal_soc_state_max: in dml2_core_internal_soc_state_type_str()
2769 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max], in calculate_bandwidth_available() argument
2770 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max], in calculate_bandwidth_available()
2771 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max], // min between SDP and DRAM in calculate_bandwidth_available() argument
2772 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max], in calculate_bandwidth_available()
2773 double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max], in calculate_bandwidth_available() argument
2774 double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max], in calculate_bandwidth_available() argument
2789 for (m = 0; m < dml2_core_internal_soc_state_max; m++) { in calculate_bandwidth_available()
2828 double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max], in calculate_avg_bandwidth_required()
2847 for (m = 0; m < dml2_core_internal_soc_state_max; m++) { in calculate_avg_bandwidth_required()
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