Searched refs:dmar_writeq (Results 1 – 6 of 6) sorted by relevance
| /linux-6.12.1/drivers/iommu/intel/ |
| D | svm.c | 70 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); in intel_svm_enable_prq()
71 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); in intel_svm_enable_prq()
72 dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER); in intel_svm_enable_prq()
93 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); in intel_svm_finish_prq()
94 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); in intel_svm_finish_prq()
95 dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL); in intel_svm_finish_prq()
501 dmar_writeq(iommu->reg + DMAR_PQH_REG, tail); in prq_event_thread()
|
| D | perfmon.c | 414 dmar_writeq(iommu_config_base(iommu_pmu, idx), hwc->config); in iommu_pmu_assign_event()
513 dmar_writeq(iommu_pmu->overflow, status); in iommu_pmu_counter_overflow()
|
| D | iommu.c | 1110 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr); in iommu_set_root_entry()
1178 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); in __iommu_flush_context()
1219 dmar_writeq(iommu->reg + tlb_offset, val_iva); in __iommu_flush_iotlb()
1220 dmar_writeq(iommu->reg + tlb_offset + 8, val); in __iommu_flush_iotlb()
4903 dmar_writeq(iommu->reg + DMAR_ECEO_REG, ob); in ecmd_submit_sync()
4904 dmar_writeq(iommu->reg + DMAR_ECMD_REG, ecmd | (oa << DMA_ECMD_OA_SHIFT)); in ecmd_submit_sync()
|
| D | iommu.h | 152 #define dmar_writeq(a,v) writeq(v,a) macro
|
| D | irq_remapping.c | 476 dmar_writeq(iommu->reg + DMAR_IRTA_REG, in iommu_set_irq_remapping()
|
| D | dmar.c | 1664 dmar_writeq(iommu->reg + DMAR_IQA_REG, val); in __dmar_enable_qi()
|