Searched refs:dm_irq_params (Results 1 – 6 of 6) sorted by relevance
94 was_activated = acrtc->dm_irq_params.window_param.activated; in amdgpu_dm_set_crc_window_default()95 acrtc->dm_irq_params.window_param.x_start = 0; in amdgpu_dm_set_crc_window_default()96 acrtc->dm_irq_params.window_param.y_start = 0; in amdgpu_dm_set_crc_window_default()97 acrtc->dm_irq_params.window_param.x_end = 0; in amdgpu_dm_set_crc_window_default()98 acrtc->dm_irq_params.window_param.y_end = 0; in amdgpu_dm_set_crc_window_default()99 acrtc->dm_irq_params.window_param.activated = false; in amdgpu_dm_set_crc_window_default()100 acrtc->dm_irq_params.window_param.update_win = false; in amdgpu_dm_set_crc_window_default()101 acrtc->dm_irq_params.window_param.skip_frame_cnt = 0; in amdgpu_dm_set_crc_window_default()136 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; in amdgpu_dm_crtc_notify_ta_to_read()175 stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream; in amdgpu_dm_forward_crc_window()[all …]
31 struct dm_irq_params { struct
3492 acrtc->dm_irq_params.window_param.x_start = (uint16_t) val; in crc_win_x_start_set()3493 acrtc->dm_irq_params.window_param.update_win = false; in crc_win_x_start_set()3509 *val = acrtc->dm_irq_params.window_param.x_start; in crc_win_x_start_get()3529 acrtc->dm_irq_params.window_param.y_start = (uint16_t) val; in crc_win_y_start_set()3530 acrtc->dm_irq_params.window_param.update_win = false; in crc_win_y_start_set()3546 *val = acrtc->dm_irq_params.window_param.y_start; in crc_win_y_start_get()3565 acrtc->dm_irq_params.window_param.x_end = (uint16_t) val; in crc_win_x_end_set()3566 acrtc->dm_irq_params.window_param.update_win = false; in crc_win_x_end_set()3582 *val = acrtc->dm_irq_params.window_param.x_end; in crc_win_x_end_get()3601 acrtc->dm_irq_params.window_param.y_end = (uint16_t) val; in crc_win_y_end_set()[all …]
71 return acrtc->dm_irq_params.freesync_config.state == in amdgpu_dm_crtc_vrr_active_irq()73 acrtc->dm_irq_params.freesync_config.state == in amdgpu_dm_crtc_vrr_active_irq()272 vblank_work->acrtc->dm_irq_params.allow_sr_entry); in amdgpu_dm_crtc_vblank_control_worker()
271 if (!acrtc->dm_irq_params.stream) { in dm_vblank_get_counter()277 return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream); in dm_vblank_get_counter()292 if (!acrtc->dm_irq_params.stream) { in dm_crtc_get_scanoutpos()305 dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream, in dm_crtc_get_scanoutpos()474 !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start, in dm_pflip_high_irq()519 amdgpu_crtc->dm_irq_params.last_flip_vblank = in dm_pflip_high_irq()571 if (acrtc->dm_irq_params.stream && in dm_vupdate_high_irq()576 acrtc->dm_irq_params.stream, in dm_vupdate_high_irq()577 &acrtc->dm_irq_params.vrr_params); in dm_vupdate_high_irq()581 acrtc->dm_irq_params.stream, in dm_vupdate_high_irq()[all …]
486 struct dm_irq_params dm_irq_params; member