| /linux-6.12.1/drivers/gpu/drm/rockchip/ |
| D | rockchip_vop2_reg.c | 188 .dly = { 20, 47, 41 },
201 .dly = { 20, 47, 41 },
214 .dly = { 20, 47, 41 },
227 .dly = { 20, 47, 41 },
240 .dly = { 0, 27, 21 },
256 .dly = { 0, 27, 21 },
338 .dly = { 4, 26, 29 },
354 .dly = { 4, 26, 29 },
369 .dly = { 4, 26, 29 },
384 .dly = { 4, 26, 29 },
[all …]
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| D | rockchip_drm_vop2.c | 2426 u32 dly; in vop2_setup_dly_for_windows() local
2429 dly = win->delay; in vop2_setup_dly_for_windows()
2433 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_0, dly); in vop2_setup_dly_for_windows()
2434 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_1, dly); in vop2_setup_dly_for_windows()
2437 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_0, dly); in vop2_setup_dly_for_windows()
2438 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_1, dly); in vop2_setup_dly_for_windows()
2441 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART0, dly); in vop2_setup_dly_for_windows()
2444 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly); in vop2_setup_dly_for_windows()
2447 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly); in vop2_setup_dly_for_windows()
2450 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly); in vop2_setup_dly_for_windows()
[all …]
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| D | rockchip_drm_vop2.h | 145 const u8 dly[VOP2_DLY_MODE_MAX]; member
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| /linux-6.12.1/arch/mips/boot/dts/cavium-octeon/ |
| D | octeon_3xxx.dtsi | 140 cavium,t-rd-dly = <0>;
157 cavium,t-rd-dly = <0>;
174 cavium,t-rd-dly = <0>;
191 cavium,t-rd-dly = <0>;
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| D | octeon_68xx.dts | 476 cavium,t-rd-dly = <0>;
493 cavium,t-rd-dly = <0>;
510 cavium,t-rd-dly = <0>;
527 cavium,t-rd-dly = <0>;
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| /linux-6.12.1/Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
97 cavium,t-rd-dly = <0>;
117 cavium,t-rd-dly = <0>;
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| /linux-6.12.1/drivers/mmc/host/ |
| D | meson-gx-mmc.c | 529 unsigned int val, dly, max_dly, i; in meson_mmc_resampling_tuning() local
541 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1; in meson_mmc_resampling_tuning()
543 dly = 0; in meson_mmc_resampling_tuning()
547 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly); in meson_mmc_resampling_tuning()
553 (dly + i) % max_dly); in meson_mmc_resampling_tuning()
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| D | sdhci-pci-core.c | 1000 u32 dly; in glk_rpm_retune_wa() local
1022 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + in glk_rpm_retune_wa()
1024 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) in glk_rpm_retune_wa()
1027 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; in glk_rpm_retune_wa()
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| /linux-6.12.1/drivers/input/keyboard/ |
| D | tegra-kbc.c | 251 unsigned long dly; in tegra_kbc_keypress_timer() local
259 dly = (val == 1) ? kbc->repoll_dly : 1; in tegra_kbc_keypress_timer()
260 mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly)); in tegra_kbc_keypress_timer()
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| /linux-6.12.1/drivers/soc/mediatek/ |
| D | mtk-pmic-wrap.c | 1646 signed char dly[16] = { in pwrap_init_sidly() local
1660 if (dly[pass] < 0) { in pwrap_init_sidly()
1666 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY); in pwrap_init_sidly()
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| /linux-6.12.1/drivers/crypto/intel/qat/qat_common/ |
| D | qat_hal.c | 1388 const unsigned short gprnum = 0, dly = num_inst * 0x5; in qat_hal_put_rel_wr_xfer() local
1426 code_off, dly, NULL); in qat_hal_put_rel_wr_xfer()
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