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/linux-6.12.1/drivers/clk/tegra/
Dclk-divider.c21 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
38 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local
43 reg = readl_relaxed(divider->reg); in clk_frac_div_recalc_rate()
45 if ((divider->flags & TEGRA_DIVIDER_UART) && in clk_frac_div_recalc_rate()
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
51 mul = get_mul(divider); in clk_frac_div_recalc_rate()
64 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_round_rate() local
71 div = get_div(divider, rate, output_rate); in clk_frac_div_round_rate()
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/linux-6.12.1/drivers/clk/ti/
Ddivider.c32 static void _setup_mask(struct clk_omap_divider *divider) in _setup_mask() argument
38 if (divider->table) { in _setup_mask()
41 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
45 max_val = divider->max; in _setup_mask()
47 if (!(divider->flags & CLK_DIVIDER_ONE_BASED) && in _setup_mask()
48 !(divider->flags & CLK_DIVIDER_POWER_OF_TWO)) in _setup_mask()
52 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in _setup_mask()
57 divider->mask = (1 << fls(mask)) - 1; in _setup_mask()
60 static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val) in _get_div() argument
62 if (divider->flags & CLK_DIVIDER_ONE_BASED) in _get_div()
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Dclk-dra7-atl.c49 u32 divider; /* Cached divider value */ member
85 cdesc->divider - 1); in atl_clk_enable()
120 return parent_rate / cdesc->divider; in atl_clk_recalc_rate()
126 unsigned divider; in atl_clk_round_rate() local
128 divider = (*parent_rate + rate / 2) / rate; in atl_clk_round_rate()
129 if (divider > DRA7_ATL_DIVIDER_MASK + 1) in atl_clk_round_rate()
130 divider = DRA7_ATL_DIVIDER_MASK + 1; in atl_clk_round_rate()
132 return *parent_rate / divider; in atl_clk_round_rate()
139 u32 divider; in atl_clk_set_rate() local
145 divider = ((parent_rate + rate / 2) / rate) - 1; in atl_clk_set_rate()
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/linux-6.12.1/drivers/clk/qcom/
Dclk-regmap-divider.c21 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_ro_rate() local
22 struct clk_regmap *clkr = &divider->clkr; in div_round_ro_rate()
25 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate()
26 val >>= divider->shift; in div_round_ro_rate()
27 val &= BIT(divider->width) - 1; in div_round_ro_rate()
29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate()
36 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local
38 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate()
45 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_set_rate() local
46 struct clk_regmap *clkr = &divider->clkr; in div_set_rate()
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/linux-6.12.1/drivers/clk/mvebu/
Ddove-divider.c53 unsigned int divider; in dove_get_divider() local
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
64 return divider; in dove_get_divider()
70 unsigned int divider, max; in dove_calc_divider() local
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in dove_calc_divider()
78 if (divider == dc->divider_table[i]) { in dove_calc_divider()
79 divider = i; in dove_calc_divider()
88 if (set && (divider == 0 || divider >= max)) in dove_calc_divider()
90 if (divider >= max) in dove_calc_divider()
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/linux-6.12.1/drivers/clk/
Dclk-divider.c29 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
31 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
32 return ioread32be(divider->reg); in clk_div_readl()
34 return readl(divider->reg); in clk_div_readl()
37 static inline void clk_div_writel(struct clk_divider *divider, u32 val) in clk_div_writel() argument
39 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_writel()
40 iowrite32be(val, divider->reg); in clk_div_writel()
42 writel(val, divider->reg); in clk_div_writel()
152 struct clk_divider *divider = to_clk_divider(hw); in clk_divider_recalc_rate() local
155 val = clk_div_readl(divider) >> divider->shift; in clk_divider_recalc_rate()
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Dclk-milbeaut.c379 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_recalc_rate() local
382 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_recalc_rate()
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()
385 return divider_recalc_rate(hw, parent_rate, val, divider->table, in m10v_clk_divider_recalc_rate()
386 divider->flags, divider->width); in m10v_clk_divider_recalc_rate()
392 struct m10v_clk_divider *divider = to_m10v_div(hw); in m10v_clk_divider_round_rate() local
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in m10v_clk_divider_round_rate()
398 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_round_rate()
399 val &= clk_div_mask(divider->width); in m10v_clk_divider_round_rate()
401 return divider_ro_round_rate(hw, rate, prate, divider->table, in m10v_clk_divider_round_rate()
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/linux-6.12.1/drivers/clk/xilinx/
Dclk-xlnx-clock-wizard.c194 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); in clk_wzrd_recalc_rate_ver() local
195 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_recalc_rate_ver()
219 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); in clk_wzrd_recalc_rate() local
220 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_recalc_rate()
223 val = readl(div_addr) >> divider->shift; in clk_wzrd_recalc_rate()
224 val &= div_mask(divider->width); in clk_wzrd_recalc_rate()
226 return divider_recalc_rate(hw, parent_rate, val, divider->table, in clk_wzrd_recalc_rate()
227 divider->flags, divider->width); in clk_wzrd_recalc_rate()
233 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw); in clk_wzrd_ver_dynamic_reconfig() local
234 void __iomem *div_addr = divider->base + divider->offset; in clk_wzrd_ver_dynamic_reconfig()
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/linux-6.12.1/drivers/clk/rockchip/
Dclk-half-divider.c25 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local
28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
98 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_round_rate() local
102 divider->width, in clk_half_divider_round_rate()
103 divider->flags); in clk_half_divider_round_rate()
111 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_set_rate() local
118 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
120 if (divider->lock) in clk_half_divider_set_rate()
121 spin_lock_irqsave(divider->lock, flags); in clk_half_divider_set_rate()
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/linux-6.12.1/drivers/clk/mxs/
Dclk-div.c22 struct clk_divider divider; member
30 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
90 div->divider.reg = reg; in mxs_clk_div()
91 div->divider.shift = shift; in mxs_clk_div()
92 div->divider.width = width; in mxs_clk_div()
93 div->divider.flags = CLK_DIVIDER_ONE_BASED; in mxs_clk_div()
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/linux-6.12.1/drivers/clk/imx/
Dclk-fixup-div.c24 struct clk_divider divider; member
31 struct clk_divider *divider = to_clk_divider(hw); in to_clk_fixup_div() local
33 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
41 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate()
49 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); in clk_fixup_div_round_rate()
57 unsigned int divider, value; in clk_fixup_div_set_rate() local
61 divider = parent_rate / rate; in clk_fixup_div_set_rate()
64 value = divider - 1; in clk_fixup_div_set_rate()
110 fixup_div->divider.reg = reg; in imx_clk_hw_fixup_divider()
111 fixup_div->divider.shift = shift; in imx_clk_hw_fixup_divider()
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Dclk-composite-8m.c31 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_recalc_rate() local
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
95 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_set_rate() local
107 spin_lock_irqsave(divider->lock, flags); in imx8m_clk_composite_divider_set_rate()
109 orig = readl(divider->reg); in imx8m_clk_composite_divider_set_rate()
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Dclk-composite-93.c116 struct clk_divider *divider = to_clk_divider(hw); in imx93_clk_composite_divider_set_rate() local
122 value = divider_get_val(rate, parent_rate, divider->table, divider->width, divider->flags); in imx93_clk_composite_divider_set_rate()
126 if (divider->lock) in imx93_clk_composite_divider_set_rate()
127 spin_lock_irqsave(divider->lock, flags); in imx93_clk_composite_divider_set_rate()
129 val = readl(divider->reg); in imx93_clk_composite_divider_set_rate()
130 val &= ~(clk_div_mask(divider->width) << divider->shift); in imx93_clk_composite_divider_set_rate()
131 val |= (u32)value << divider->shift; in imx93_clk_composite_divider_set_rate()
132 writel(val, divider->reg); in imx93_clk_composite_divider_set_rate()
134 ret = imx93_clk_composite_wait_ready(hw, divider->reg); in imx93_clk_composite_divider_set_rate()
136 if (divider->lock) in imx93_clk_composite_divider_set_rate()
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Dclk-divider-gate.c15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
201 div_gate->divider.reg = reg; in imx_clk_hw_divider_gate()
202 div_gate->divider.shift = shift; in imx_clk_hw_divider_gate()
203 div_gate->divider.width = width; in imx_clk_hw_divider_gate()
204 div_gate->divider.lock = lock; in imx_clk_hw_divider_gate()
205 div_gate->divider.table = table; in imx_clk_hw_divider_gate()
206 div_gate->divider.hw.init = &init; in imx_clk_hw_divider_gate()
207 div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags; in imx_clk_hw_divider_gate()
213 hw = &div_gate->divider.hw; in imx_clk_hw_divider_gate()
/linux-6.12.1/drivers/clk/stm32/
Dclk-stm32-core.c212 const struct stm32_div_cfg *divider = &data->dividers[div_id]; in stm32_divider_get_rate() local
216 val = readl(base + divider->offset) >> divider->shift; in stm32_divider_get_rate()
217 val &= clk_div_mask(divider->width); in stm32_divider_get_rate()
218 div = _get_div(divider->table, val, divider->flags, divider->width); in stm32_divider_get_rate()
221 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), in stm32_divider_get_rate()
235 const struct stm32_div_cfg *divider = &data->dividers[div_id]; in stm32_divider_set_rate() local
239 value = divider_get_val(rate, parent_rate, divider->table, in stm32_divider_set_rate()
240 divider->width, divider->flags); in stm32_divider_set_rate()
244 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { in stm32_divider_set_rate()
245 val = clk_div_mask(divider->width) << (divider->shift + 16); in stm32_divider_set_rate()
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/linux-6.12.1/drivers/clk/zynqmp/
Ddivider.c82 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_recalc_rate() local
84 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_recalc_rate()
85 u32 div_type = divider->div_type; in zynqmp_clk_divider_recalc_rate()
100 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_recalc_rate()
104 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO), in zynqmp_clk_divider_recalc_rate()
125 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw); in zynqmp_clk_divider_round_rate() local
127 u32 clk_id = divider->clk_id; in zynqmp_clk_divider_round_rate()
128 u32 div_type = divider->div_type; in zynqmp_clk_divider_round_rate()
134 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in zynqmp_clk_divider_round_rate()
145 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) in zynqmp_clk_divider_round_rate()
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/linux-6.12.1/drivers/clk/baikal-t1/
Dccu-div.c78 unsigned long divider) in ccu_div_var_update_clkdiv() argument
85 nd = ccu_div_lock_delay_ns(parent_rate, divider); in ccu_div_var_update_clkdiv()
211 unsigned long divider; in ccu_div_var_recalc_rate() local
215 divider = ccu_div_get(div->mask, val); in ccu_div_var_recalc_rate()
217 return ccu_div_calc_freq(parent_rate, divider); in ccu_div_var_recalc_rate()
224 unsigned long divider; in ccu_div_var_calc_divider() local
226 divider = parent_rate / rate; in ccu_div_var_calc_divider()
227 return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN, in ccu_div_var_calc_divider()
235 unsigned long divider; in ccu_div_var_round_rate() local
237 divider = ccu_div_var_calc_divider(rate, *parent_rate, div->mask); in ccu_div_var_round_rate()
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/linux-6.12.1/drivers/clk/sophgo/
Dclk-sg2042-clkgen.c160 struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw); in sg2042_clk_divider_recalc_rate() local
164 if (!(readl(divider->reg) & BIT(SHIFT_DIV_FACTOR_SEL))) { in sg2042_clk_divider_recalc_rate()
165 val = divider->initval; in sg2042_clk_divider_recalc_rate()
167 val = readl(divider->reg) >> divider->shift; in sg2042_clk_divider_recalc_rate()
168 val &= clk_div_mask(divider->width); in sg2042_clk_divider_recalc_rate()
172 divider->div_flags, divider->width); in sg2042_clk_divider_recalc_rate()
183 struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw); in sg2042_clk_divider_round_rate() local
188 if (divider->div_flags & CLK_DIVIDER_READ_ONLY) { in sg2042_clk_divider_round_rate()
189 if (!(readl(divider->reg) & BIT(SHIFT_DIV_FACTOR_SEL))) { in sg2042_clk_divider_round_rate()
190 bestdiv = divider->initval; in sg2042_clk_divider_round_rate()
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/linux-6.12.1/drivers/clk/davinci/
Dpll.c243 struct clk_divider *divider; in davinci_pll_div_register() local
254 divider = kzalloc(sizeof(*divider), GFP_KERNEL); in davinci_pll_div_register()
255 if (!divider) { in davinci_pll_div_register()
260 divider->reg = reg; in davinci_pll_div_register()
261 divider->shift = DIV_RATIO_SHIFT; in davinci_pll_div_register()
262 divider->width = DIV_RATIO_WIDTH; in davinci_pll_div_register()
265 divider->flags |= CLK_DIVIDER_READ_ONLY; in davinci_pll_div_register()
270 NULL, NULL, &divider->hw, divider_ops, in davinci_pll_div_register()
280 kfree(divider); in davinci_pll_div_register()
578 struct clk_divider *divider; in davinci_pll_obsclk_register() local
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/linux-6.12.1/Documentation/devicetree/bindings/clock/ti/
Ddivider.txt1 Binding for TI divider clock
4 register-mapped adjustable clock rate divider that does not gate and has
42 The binding must also provide the register to control the divider and
43 unless the divider array is provided, min and max dividers. Optionally
54 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
57 - reg : offset for register controlling adjustable divider
62 - ti,bit-shift : number of bits to shift the divider value, defaults to 0
76 - ti,latch-bit : latch the divider value to HW, only needed if the register
77 access requires this. As an example dra76x DPLL_GMAC H14 divider implements
83 compatible = "ti,divider-clock";
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/linux-6.12.1/drivers/clk/renesas/
Drzv2h-cpg.c200 struct clk_divider *divider = to_clk_divider(hw); in rzv2h_ddiv_recalc_rate() local
203 val = readl(divider->reg) >> divider->shift; in rzv2h_ddiv_recalc_rate()
204 val &= clk_div_mask(divider->width); in rzv2h_ddiv_recalc_rate()
206 return divider_recalc_rate(hw, parent_rate, val, divider->table, in rzv2h_ddiv_recalc_rate()
207 divider->flags, divider->width); in rzv2h_ddiv_recalc_rate()
213 struct clk_divider *divider = to_clk_divider(hw); in rzv2h_ddiv_round_rate() local
215 return divider_round_rate(hw, rate, prate, divider->table, in rzv2h_ddiv_round_rate()
216 divider->width, divider->flags); in rzv2h_ddiv_round_rate()
222 struct clk_divider *divider = to_clk_divider(hw); in rzv2h_ddiv_determine_rate() local
224 return divider_determine_rate(hw, req, divider->table, divider->width, in rzv2h_ddiv_determine_rate()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dxgene.txt37 reset and/or the divider. Either may be omitted, but at least
55 - divider-offset : Offset to the divider CSR register from the divider base.
57 - divider-width : Width of the divider register. Default is 0.
58 - divider-shift : Bit shift of the divider register. Default is 0.
107 divider-offset = <0x238>;
108 divider-width = <0x9>;
109 divider-shift = <0x0>;
125 divider-offset = <0x10>;
126 divider-width = <0x2>;
127 divider-shift = <0x0>;
Dkeystone-pll.txt2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
27 reg-names = "control", "multiplier", "post-divider";
64 - compatible : shall be "ti,keystone,pll-divider-clock"
68 - bit-mask : arbitrary bitmask for programming the divider
76 compatible = "ti,keystone,pll-divider-clock";
/linux-6.12.1/drivers/clk/x86/
Dclk-cgu.c125 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); in lgm_clk_divider_recalc_rate() local
128 val = lgm_get_clk_val(divider->membase, divider->reg, in lgm_clk_divider_recalc_rate()
129 divider->shift, divider->width); in lgm_clk_divider_recalc_rate()
131 return divider_recalc_rate(hw, parent_rate, val, divider->table, in lgm_clk_divider_recalc_rate()
132 divider->flags, divider->width); in lgm_clk_divider_recalc_rate()
139 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); in lgm_clk_divider_round_rate() local
141 return divider_round_rate(hw, rate, prate, divider->table, in lgm_clk_divider_round_rate()
142 divider->width, divider->flags); in lgm_clk_divider_round_rate()
149 struct lgm_clk_divider *divider = to_lgm_clk_divider(hw); in lgm_clk_divider_set_rate() local
152 value = divider_get_val(rate, prate, divider->table, in lgm_clk_divider_set_rate()
[all …]
/linux-6.12.1/drivers/i2c/busses/
Di2c-bcm2835.c93 u32 divider = DIV_ROUND_UP(parent_rate, rate); in clk_bcm2835_i2c_calc_divider() local
100 if (divider & 1) in clk_bcm2835_i2c_calc_divider()
101 divider++; in clk_bcm2835_i2c_calc_divider()
102 if ((divider < BCM2835_I2C_CDIV_MIN) || in clk_bcm2835_i2c_calc_divider()
103 (divider > BCM2835_I2C_CDIV_MAX)) in clk_bcm2835_i2c_calc_divider()
106 return divider; in clk_bcm2835_i2c_calc_divider()
114 u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate); in clk_bcm2835_i2c_set_rate() local
116 if (divider == -EINVAL) in clk_bcm2835_i2c_set_rate()
119 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider); in clk_bcm2835_i2c_set_rate()
126 fedl = max(divider / 16, 1u); in clk_bcm2835_i2c_set_rate()
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