| /linux-6.12.1/drivers/clk/imx/ |
| D | clk-pllv3.c | 52 u32 div_mask; member
115 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
143 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
163 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_sys_recalc_rate()
198 val &= ~pll->div_mask; in clk_pllv3_sys_set_rate()
220 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_av_recalc_rate()
285 val &= ~pll->div_mask; in clk_pllv3_av_set_rate()
353 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20; in clk_pllv3_vf610_recalc_rate()
376 val &= ~pll->div_mask; /* clear bit for mfi=20 */ in clk_pllv3_vf610_set_rate()
378 val |= pll->div_mask; /* set bit for mfi=22 */ in clk_pllv3_vf610_set_rate()
[all …]
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| D | clk-fixup-div.c | 12 #define div_mask(d) ((1 << (d->width)) - 1) macro
66 if (value > div_mask(div)) in clk_fixup_div_set_rate()
67 value = div_mask(div); in clk_fixup_div_set_rate()
72 val &= ~(div_mask(div) << div->shift); in clk_fixup_div_set_rate()
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| D | clk.h | 112 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \ argument
113 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
261 const char *parent_name, void __iomem *base, u32 div_mask);
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| /linux-6.12.1/drivers/clk/rockchip/ |
| D | clk-half-divider.c | 11 #define div_mask(width) ((1 << (width)) - 1) macro
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
46 maxdiv = div_mask(width); in clk_half_divider_bestdiv()
88 bestdiv = div_mask(width); in clk_half_divider_bestdiv()
118 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
126 val = div_mask(divider->width) << (divider->shift + 16); in clk_half_divider_set_rate()
129 val &= ~(div_mask(divider->width) << divider->shift); in clk_half_divider_set_rate()
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| /linux-6.12.1/drivers/clk/tegra/ |
| D | clk-utils.c | 10 #define div_mask(w) ((1 << (w)) - 1) macro
39 if (divider_ux1 > div_mask(width)) in div_frac_get()
40 return div_mask(width); in div_frac_get()
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| D | clk-divider.c | 15 #define div_mask(d) ((1 << (d->width)) - 1) macro
17 #define get_max_div(d) div_mask(d)
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
96 val &= ~(div_mask(divider) << divider->shift); in clk_frac_div_set_rate()
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| /linux-6.12.1/sound/soc/fsl/ |
| D | fsl_mqs.c | 60 int div_mask; member
100 mqs_priv->soc->div_mask, in fsl_mqs_hw_params()
316 .div_mask = MQS_CLK_DIV_MASK,
329 .div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK,
342 .div_mask = GENMASK(15, 8),
355 .div_mask = GENMASK(15, 8),
368 .div_mask = GENMASK(16, 9),
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| /linux-6.12.1/sound/soc/mediatek/mt8192/ |
| D | mt8192-afe-clk.c | 412 int div_mask; member
427 .div_mask = APLL12_CK_DIV0_MASK,
440 .div_mask = APLL12_CK_DIV1_MASK,
453 .div_mask = APLL12_CK_DIV2_MASK,
466 .div_mask = APLL12_CK_DIV3_MASK,
479 .div_mask = APLL12_CK_DIV4_MASK,
492 .div_mask = APLL12_CK_DIVB_MASK,
502 .div_mask = APLL12_CK_DIV5_MASK,
515 .div_mask = APLL12_CK_DIV6_MASK,
528 .div_mask = APLL12_CK_DIV7_MASK,
[all …]
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| /linux-6.12.1/drivers/clk/hisilicon/ |
| D | clkdivider-hi6220.c | 19 #define div_mask(width) ((1 << (width)) - 1) macro
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
82 data &= ~(div_mask(dclk->width) << dclk->shift); in hi6220_clkdiv_set_rate()
117 max_div = div_mask(width) + 1; in hi6220_register_clkdiv()
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| /linux-6.12.1/drivers/i2c/busses/ |
| D | i2c-brcmstb.c | 83 u32 div_mask; member
115 .div_mask = 0
120 .div_mask = 0
125 .div_mask = 0
130 .div_mask = 0
135 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
140 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
145 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
150 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
562 bsc_clk[i].div_mask); in brcmstb_i2c_set_bus_speed()
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| /linux-6.12.1/drivers/clk/ |
| D | clk-vt8500.c | 23 unsigned int div_mask; member
118 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
121 if ((cdev->div_mask == 0x3F) && (div & BIT(5))) in vt8500_dclk_recalc_rate()
126 div = (cdev->div_mask + 1); in vt8500_dclk_recalc_rate()
150 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_round_rate()
169 if (divisor == cdev->div_mask + 1) in vt8500_dclk_set_rate()
173 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_set_rate()
181 if (divisor > cdev->div_mask) { in vt8500_dclk_set_rate()
262 dev_clk->div_mask = 0x1f; in vtwm_device_clk_init()
264 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); in vtwm_device_clk_init()
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| /linux-6.12.1/drivers/clk/actions/ |
| D | owl-factor.c | 157 val &= div_mask(factor_hw); in owl_factor_helper_recalc_rate()
192 if (val > div_mask(factor_hw)) in owl_factor_helper_set_rate()
193 val = div_mask(factor_hw); in owl_factor_helper_set_rate()
197 reg &= ~(div_mask(factor_hw) << factor_hw->shift); in owl_factor_helper_set_rate()
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| D | owl-factor.h | 58 #define div_mask(d) ((1 << ((d)->width)) - 1) macro
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| /linux-6.12.1/include/linux/ |
| D | sh_clk.h | 60 unsigned int div_mask; member
157 .div_mask = SH_CLK_DIV4_MSK, \
181 .div_mask = SH_CLK_DIV6_MSK, \
193 .div_mask = SH_CLK_DIV6_MSK, \
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| /linux-6.12.1/drivers/sh/clk/ |
| D | cpg.c | 123 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
139 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
152 if (clk->div_mask == SH_CLK_DIV6_MSK) { in sh_clk_div_enable()
175 val |= clk->div_mask; in sh_clk_div_disable()
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| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk-cpu.c | 281 unsigned long div = 0, div_mask = DIV_MASK; in exynos_cpuclk_post_rate_change() local
303 div_mask |= E4210_DIV0_ATB_MASK; in exynos_cpuclk_post_rate_change()
306 exynos_set_safe_div(cpuclk, div, div_mask); in exynos_cpuclk_post_rate_change()
390 unsigned long div = 0, div_mask = DIV_MASK; in exynos5433_cpuclk_post_rate_change() local
401 exynos_set_safe_div(cpuclk, div, div_mask); in exynos5433_cpuclk_post_rate_change()
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| /linux-6.12.1/drivers/clk/mmp/ |
| D | clk-mix.c | 26 unsigned int div_mask = (1 << mix->reg_info.width_div) - 1; in _get_maxdiv() local
31 return div_mask; in _get_maxdiv()
33 return 1 << div_mask; in _get_maxdiv()
40 return div_mask + 1; in _get_maxdiv()
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| /linux-6.12.1/drivers/clk/at91/ |
| D | clk-peripheral.c | 176 periph->layout->div_mask | periph->layout->cmd | in clk_sam9x5_peripheral_set()
178 field_prep(periph->layout->div_mask, periph->div) | in clk_sam9x5_peripheral_set()
245 periph->div = field_get(periph->layout->div_mask, status); in clk_sam9x5_peripheral_recalc_rate()
487 if (layout->div_mask) in at91_clk_register_sam9x5_peripheral()
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| D | clk-sam9x60-pll.c | 350 core->layout->div_mask | ena_msk, in sam9x60_div_pll_set_div()
372 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_set()
465 for (divid = 1; divid < core->layout->div_mask; divid++) { in sam9x60_div_pll_compute_div()
524 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift; in sam9x60_div_pll_set_rate_chg()
580 cdiv = (val & core.layout->div_mask) >> core.layout->div_shift; in sam9x60_div_pll_notifier_fn()
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| D | pmc.h | 61 u32 div_mask; member
100 u32 div_mask; member
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| D | sam9x7.c | 160 .div_mask = GENMASK(7, 0),
168 .div_mask = GENMASK(7, 0),
177 .div_mask = GENMASK(19, 12),
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| D | at91sam9n12.c | 76 .div_mask = GENMASK(17, 16),
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| /linux-6.12.1/drivers/clk/nxp/ |
| D | clk-lpc32xx.c | 920 #define div_mask(width) ((1 << (width)) - 1) macro
952 val &= div_mask(divider->width); in clk_divider_recalc_rate()
968 bestdiv &= div_mask(divider->width); in clk_divider_round_rate()
988 div_mask(divider->width) << divider->shift, in clk_divider_set_rate()
1475 static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate) in lpc32xx_clk_div_quirk() argument
1481 if (!(val & div_mask)) { in lpc32xx_clk_div_quirk()
1483 val |= BIT(__ffs(div_mask)); in lpc32xx_clk_div_quirk()
1486 regmap_update_bits(clk_regmap, reg, gate | div_mask, val); in lpc32xx_clk_div_quirk()
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| /linux-6.12.1/drivers/mfd/ |
| D | db8500-prcmu.c | 522 u32 div_mask; member
529 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
534 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
539 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
645 u32 div_mask; in prcmu_config_clkout() local
655 div_mask = PRCM_CLKOCR_CLKODIV0_MASK; in prcmu_config_clkout()
660 div_mask = PRCM_CLKOCR_CLKODIV1_MASK; in prcmu_config_clkout()
671 if (val & div_mask) { in prcmu_config_clkout()
678 if ((val & mask & ~div_mask) != bits) { in prcmu_config_clkout()
1534 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/msm/dsi/phy/ |
| D | dsi_phy_14nm.c | 604 #define div_mask(width) ((1 << (width)) - 1) macro
618 val &= div_mask(width); in dsi_pll_14nm_postdiv_recalc_rate()
660 val &= ~(div_mask(width) << shift); in dsi_pll_14nm_postdiv_set_rate()
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