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Searched refs:dev_cap (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/net/ethernet/mellanox/mlx4/
Dfw.c725 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) in mlx4_QUERY_DEV_CAP() argument
832 dev_cap->flags2 = 0; in mlx4_QUERY_DEV_CAP()
846 dev_cap->map_clock_to_user = field & 0x80; in mlx4_QUERY_DEV_CAP()
848 dev_cap->reserved_qps = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
850 dev_cap->max_qps = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
852 dev_cap->reserved_srqs = 1 << (field >> 4); in mlx4_QUERY_DEV_CAP()
854 dev_cap->max_srqs = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
856 dev_cap->max_cq_sz = 1 << field; in mlx4_QUERY_DEV_CAP()
858 dev_cap->reserved_cqs = 1 << (field & 0xf); in mlx4_QUERY_DEV_CAP()
860 dev_cap->max_cqs = 1 << (field & 0x1f); in mlx4_QUERY_DEV_CAP()
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Dprofile.c71 struct mlx4_dev_cap *dev_cap, in mlx4_make_profile() argument
111 profile[MLX4_RES_QP].size = dev_cap->qpc_entry_sz; in mlx4_make_profile()
112 profile[MLX4_RES_RDMARC].size = dev_cap->rdmarc_entry_sz; in mlx4_make_profile()
113 profile[MLX4_RES_ALTC].size = dev_cap->altc_entry_sz; in mlx4_make_profile()
114 profile[MLX4_RES_AUXC].size = dev_cap->aux_entry_sz; in mlx4_make_profile()
115 profile[MLX4_RES_SRQ].size = dev_cap->srq_entry_sz; in mlx4_make_profile()
116 profile[MLX4_RES_CQ].size = dev_cap->cqc_entry_sz; in mlx4_make_profile()
117 profile[MLX4_RES_EQ].size = dev_cap->eqc_entry_sz; in mlx4_make_profile()
118 profile[MLX4_RES_DMPT].size = dev_cap->dmpt_entry_sz; in mlx4_make_profile()
119 profile[MLX4_RES_CMPT].size = dev_cap->cmpt_entry_sz; in mlx4_make_profile()
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Dmain.c289 struct mlx4_dev_cap *dev_cap) in mlx4_set_num_reserved_uars() argument
298 dev_cap->reserved_uars / in mlx4_set_num_reserved_uars()
338 static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) in mlx4_query_func() argument
349 dev_cap->max_eqs = func.max_eq; in mlx4_query_func()
350 dev_cap->reserved_eqs = func.rsvd_eqs; in mlx4_query_func()
351 dev_cap->reserved_uars = func.rsvd_uars; in mlx4_query_func()
359 struct mlx4_caps *dev_cap = &dev->caps; in mlx4_enable_cqe_eqe_stride() local
362 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) || in mlx4_enable_cqe_eqe_stride()
363 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) in mlx4_enable_cqe_eqe_stride()
369 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) || in mlx4_enable_cqe_eqe_stride()
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Dfw.h230 void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
231 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap);
Dmlx4.h1068 struct mlx4_dev_cap *dev_cap,
/linux-6.12.1/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_dev.c52 struct hinic_dev_cap *dev_cap) in parse_capability() argument
57 if (!HINIC_IS_VF(hwdev->hwif) && dev_cap->intr_type != INTR_MSIX_TYPE) in parse_capability()
71 nic_cap->max_qps = dev_cap->max_sqs + 1; in parse_capability()
73 nic_cap->max_qps = dev_cap->max_sqs; in parse_capability()
79 nic_cap->max_vf = dev_cap->max_vf; in parse_capability()
80 nic_cap->max_vf_qps = dev_cap->max_vf_sqs + 1; in parse_capability()
83 hwdev->port_id = dev_cap->port_id; in parse_capability()
99 struct hinic_dev_cap dev_cap; in get_capability() local
103 out_len = sizeof(dev_cap); in get_capability()
106 HINIC_CFG_NIC_CAP, &dev_cap, sizeof(dev_cap), in get_capability()
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Dhinic_sriov.c1080 struct hinic_dev_cap *dev_cap = buf_out; in cfg_mbx_pf_proc_vf_msg() local
1085 memset(dev_cap, 0, sizeof(*dev_cap)); in cfg_mbx_pf_proc_vf_msg()
1087 dev_cap->max_vf = cap->max_vf; in cfg_mbx_pf_proc_vf_msg()
1088 dev_cap->max_sqs = cap->max_vf_qps; in cfg_mbx_pf_proc_vf_msg()
1089 dev_cap->max_rqs = cap->max_vf_qps; in cfg_mbx_pf_proc_vf_msg()
1090 dev_cap->port_id = dev->port_id; in cfg_mbx_pf_proc_vf_msg()
1092 *out_size = sizeof(*dev_cap); in cfg_mbx_pf_proc_vf_msg()
/linux-6.12.1/include/linux/mlx4/
Ddevice.h52 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \ argument
53 (dev_cap).num_ports * MIN_MSIX_P_PORT)