Home
last modified time | relevance | path

Searched refs:dcn (Results 1 – 25 of 46) sorted by relevance

12

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/
Ddml21_wrapper.c129 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml21_calculate_rq_and_dlg_params()
132 …memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.ar… in dml21_calculate_rq_and_dlg_params()
135 …context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_reg… in dml21_calculate_rq_and_dlg_params()
137 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
138 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
139 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
169 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dml21_calculate_rq_and_dlg_params()
170 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dml21_calculate_rq_and_dlg_params()
172 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in dml21_calculate_rq_and_dlg_params()
175 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispc… in dml21_calculate_rq_and_dlg_params()
[all …]
Ddml21_utils.c264 context->bw_ctx.bw.dcn.mall_ss_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
268 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
330 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz) in dml21_program_dc_pipe()
331 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz; in dml21_program_dc_pipe()
334 …memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[pipe_ctx->pipe_idx], &pln_prog->mcache_allocatio… in dml21_program_dc_pipe()
485 …memset(&context->bw_ctx.bw.dcn.fams2_stream_params, 0, sizeof(struct dmub_fams2_stream_static_stat… in dml21_build_fams2_programming()
486 …memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config)… in dml21_build_fams2_programming()
494 …struct dmub_fams2_stream_static_state *static_state = &context->bw_ctx.bw.dcn.fams2_stream_params[… in dml21_build_fams2_programming()
571 memcpy(&context->bw_ctx.bw.dcn.fams2_global_config, in dml21_build_fams2_programming()
575 context->bw_ctx.bw.dcn.fams2_global_config.num_streams = num_fams2_streams; in dml21_build_fams2_programming()
[all …]
Ddml21_translation_helper.c1028 …context->bw_ctx.bw.dcn.clk.dispclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4… in dml21_copy_clocks_to_dc_state()
1029 …context->bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x… in dml21_copy_clocks_to_dc_state()
1030 …context->bw_ctx.bw.dcn.clk.dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4… in dml21_copy_clocks_to_dc_state()
1031 …context->bw_ctx.bw.dcn.clk.fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.a… in dml21_copy_clocks_to_dc_state()
1032 …context->bw_ctx.bw.dcn.clk.idle_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks… in dml21_copy_clocks_to_dc_state()
1033 …context->bw_ctx.bw.dcn.clk.idle_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dc… in dml21_copy_clocks_to_dc_state()
1034 …context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = in_ctx->v21.mode_programming.programming->min_c… in dml21_copy_clocks_to_dc_state()
1035 …context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx->v21.mode_programming.programming-… in dml21_copy_clocks_to_dc_state()
1036 …context->bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx->v21.mode_programming.programming->uclk… in dml21_copy_clocks_to_dc_state()
1037 …context->bw_ctx.bw.dcn.clk.dtbclk_en = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.… in dml21_copy_clocks_to_dc_state()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/
Ddml2_utils.c184 context->bw_ctx.bw.dcn.clk.dispclk_khz = out_clks->dispclk_khz; in dml2_copy_clocks_to_dc_state()
185 context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz; in dml2_copy_clocks_to_dc_state()
186 context->bw_ctx.bw.dcn.clk.dramclk_khz = out_clks->uclk_mts / 16; in dml2_copy_clocks_to_dc_state()
187 context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz; in dml2_copy_clocks_to_dc_state()
188 context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz; in dml2_copy_clocks_to_dc_state()
189 context->bw_ctx.bw.dcn.clk.socclk_khz = out_clks->socclk_khz; in dml2_copy_clocks_to_dc_state()
190 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = out_clks->ref_dtbclk_khz; in dml2_copy_clocks_to_dc_state()
191 context->bw_ctx.bw.dcn.clk.p_state_change_support = out_clks->p_state_supported; in dml2_copy_clocks_to_dc_state()
285 …context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCL… in dml2_calculate_rq_and_dlg_params()
286 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml2_calculate_rq_and_dlg_params()
[all …]
Ddml2_wrapper.c446 display_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in optimize_pstate_with_svp_and_drr()
447 display_state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid = false; in optimize_pstate_with_svp_and_drr()
459 display_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true; in optimize_pstate_with_svp_and_drr()
499 display_state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid = true; in optimize_pstate_with_svp_and_drr()
500 display_state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index = drr_display_index; in optimize_pstate_with_svp_and_drr()
525 display_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in optimize_pstate_with_svp_and_drr()
526 display_state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid = false; in optimize_pstate_with_svp_and_drr()
585 context->bw_ctx.bw.dcn.clk.dtbclk_en = false; in dml2_validate_and_build_resource()
643 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(in_dc, context); in dml2_validate_and_build_resource()
651 dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.a, &dml2->v20.dml_core_ctx); in dml2_validate_and_build_resource()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddcn30_fpu.c371 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || in dcn30_fpu_update_soc_for_wm_a()
394 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn30_fpu_calculate_wm_and_dlg()
405 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = in dcn30_fpu_calculate_wm_and_dlg()
408 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
445 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
446 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn30_fpu_calculate_wm_and_dlg()
447 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn30_fpu_calculate_wm_and_dlg()
448 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn30_fpu_calculate_wm_and_dlg()
449 …context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_fpu_calculate_wm_and_dlg()
450 …context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn30_fpu_calculate_wm_and_dlg()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddcn31_fpu.c502 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0 in dcn31_calculate_wm_and_dlg_fp()
523 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
524 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn31_calculate_wm_and_dlg_fp()
525 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn31_calculate_wm_and_dlg_fp()
526 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn31_calculate_wm_and_dlg_fp()
527 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus… in dcn31_calculate_wm_and_dlg_fp()
528 …context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&cont… in dcn31_calculate_wm_and_dlg_fp()
529 …context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn31_calculate_wm_and_dlg_fp()
530 …context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->b… in dcn31_calculate_wm_and_dlg_fp()
531 …context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&… in dcn31_calculate_wm_and_dlg_fp()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/core/
Ddc_debug.c353 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
354 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
355 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
356 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
357 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
358 context->bw_ctx.bw.dcn.clk.socclk_khz); in context_clock_trace()
361 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
362 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
363 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
364 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/calcs/
Ddcn_calcs.c566 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
568 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
570 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
572 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
573 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
580 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
582 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
584 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
586 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
587 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddcn20_fpu.c1154 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
1155 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
1156 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
1157 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
1159 if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz) in dcn20_calculate_dlg_params()
1160 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz; in dcn20_calculate_dlg_params()
1162 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn20_calculate_dlg_params()
1163 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn20_calculate_dlg_params()
1164 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn20_calculate_dlg_params()
1171 …context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_swit… in dcn20_calculate_dlg_params()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddcn32_fpu.c1655 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn32_calculate_dlg_params()
1656 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn32_calculate_dlg_params()
1657 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn32_calculate_dlg_params()
1658 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn32_calculate_dlg_params()
1659 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; in dcn32_calculate_dlg_params()
1660 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn32_calculate_dlg_params()
1661 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn32_calculate_dlg_params()
1668 …context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_swit… in dcn32_calculate_dlg_params()
1670 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dcn32_calculate_dlg_params()
1671 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context); in dcn32_calculate_dlg_params()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks()
349 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks_fpga()
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
459 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
462 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
465 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; in dcn2_get_clock()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
Ddcn401_hwseq.c53 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
1273 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; in dcn401_calculate_cab_allocation()
1401 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn401_prepare_bandwidth()
1407 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn401_prepare_bandwidth()
1412 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn401_prepare_bandwidth()
1426 &context->bw_ctx.bw.dcn.watermarks, in dcn401_prepare_bandwidth()
1432 compbuf_size = context->bw_ctx.bw.dcn.arb_regs.compbuf_size; in dcn401_prepare_bandwidth()
1433 …dc->wm_optimized_required |= (compbuf_size != dc->current_state->bw_ctx.bw.dcn.arb_regs.compbuf_si… in dcn401_prepare_bandwidth()
1444 if (p_state_change_support != context->bw_ctx.bw.dcn.clk.p_state_change_support) { in dcn401_prepare_bandwidth()
1447 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support; in dcn401_prepare_bandwidth()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer_debug.c476 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_get_clock_states()
477 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_get_clock_states()
478 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_get_clock_states()
479 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_get_clock_states()
480 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_get_clock_states()
481 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_get_clock_states()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn301/
Ddcn301_fpu.c434 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn301_fpu_calculate_wm_and_dlg()
439 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, in dcn301_fpu_calculate_wm_and_dlg()
444 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, in dcn301_fpu_calculate_wm_and_dlg()
450 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, in dcn301_fpu_calculate_wm_and_dlg()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/
Ddcn32_resource_helpers.c94 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) { in dcn32_helper_calculate_num_ways_for_subvp()
98 …return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_s… in dcn32_helper_calculate_num_ways_for_subvp()
533 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down) in dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch()
778 …if (dcn32_subvp_in_use(dc, context) && context->bw_ctx.bw.dcn.clk.dcfclk_khz <= MIN_SUBVP_DCFCLK_K… in dcn32_override_min_req_dcfclk()
779 context->bw_ctx.bw.dcn.clk.dcfclk_khz = MIN_SUBVP_DCFCLK_KHZ; in dcn32_override_min_req_dcfclk()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
Ddcn32_hwseq.c226 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; in dcn32_calculate_cab_allocation()
746 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn32_initialize_min_clocks()
1825 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn32_prepare_bandwidth()
1829 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switchin… in dcn32_prepare_bandwidth()
1831 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn32_prepare_bandwidth()
1836 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn32_prepare_bandwidth()
1841 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) in dcn32_prepare_bandwidth()
1844 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || dc->clk_mgr->clks.fw_based_mclk_switchin… in dcn32_prepare_bandwidth()
1848 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support; in dcn32_prepare_bandwidth()
1882 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); in dcn32_program_outstanding_updates()
/linux-6.12.1/Documentation/gpu/amdgpu/display/
Dindex.rst91 dcn-overview.rst
92 dcn-blocks.rst
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/
Ddcn401_clk_mgr.c406 mall_ss_size_bytes = context->bw_ctx.bw.dcn.mall_ss_size_bytes; in dcn401_auto_dpm_test_log()
622 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn401_update_clocks_legacy()
1377 &context->bw_ctx.bw.dcn.clk, in dcn401_update_clocks()
1386 &context->bw_ctx.bw.dcn.clk, in dcn401_update_clocks()
1393 dcn401_auto_dpm_test_log(&context->bw_ctx.bw.dcn.clk, TO_CLK_MGR_INTERNAL(clk_mgr_base), context); in dcn401_update_clocks()
1490 new_clocks.dramclk_khz = context->bw_ctx.bw.dcn.clk.dramclk_khz; in dcn401_set_hard_min_memclk()
1491 new_clocks.idle_dramclk_khz = context->bw_ctx.bw.dcn.clk.idle_dramclk_khz; in dcn401_set_hard_min_memclk()
1492 new_clocks.p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn401_set_hard_min_memclk()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
Ddcn20_hwseq.c2341 unsigned int cache_wm_a = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns; in dcn20_prepare_bandwidth()
2354 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn20_prepare_bandwidth()
2364 &context->bw_ctx.bw.dcn.watermarks, in dcn20_prepare_bandwidth()
2370 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = cache_wm_a; in dcn20_prepare_bandwidth()
2378 compbuf_size_kb = context->bw_ctx.bw.dcn.compbuf_size_kb; in dcn20_prepare_bandwidth()
2379 …dc->wm_optimized_required |= (compbuf_size_kb != dc->current_state->bw_ctx.bw.dcn.compbuf_size_kb); in dcn20_prepare_bandwidth()
2398 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 4U * 1000U * 1000U * 1000U; in dcn20_optimize_bandwidth()
2405 &context->bw_ctx.bw.dcn.watermarks, in dcn20_optimize_bandwidth()
2411 context->bw_ctx.bw.dcn.clk.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn20_optimize_bandwidth()
2416 hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true); in dcn20_optimize_bandwidth()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
Ddcn10_hwseq.c524 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_log_hw_state()
525 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_log_hw_state()
526 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_log_hw_state()
527 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_log_hw_state()
528 dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz, in dcn10_log_hw_state()
529 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_log_hw_state()
530 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_log_hw_state()
1559 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz; in dcn10_init_hw()
1560 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz; in dcn10_init_hw()
2809 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn10_update_dchubp_dpp()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
Ddcn30_hwseq.c429 …mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info-… in dcn30_set_writeback()
1152 dc->current_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) && in dcn30_hardware_release()
1173 …if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && !dc->clk_mgr->clks.fw_based_mclk_switchi… in dcn30_prepare_bandwidth()
1175 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn30_prepare_bandwidth()
1180 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn30_prepare_bandwidth()
/linux-6.12.1/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_helpers.c1228 dc_state->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dm_helpers_dp_handle_test_pattern_request()
1229 dc_state->bw_ctx.bw.dcn.clk.dramclk_khz = clk_mgr->dc_mode_softmax_enabled ? in dm_helpers_dp_handle_test_pattern_request()
1231 dc_state->bw_ctx.bw.dcn.clk.idle_dramclk_khz = dc_state->bw_ctx.bw.dcn.clk.dramclk_khz; in dm_helpers_dp_handle_test_pattern_request()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/
Ddc_dmub_srv.c920 wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns * in dc_dmub_setup_subvp_dmub_command()
1706 …memcpy(&global_cmd->config.global, &context->bw_ctx.bw.dcn.fams2_global_config, sizeof(struct dmub… in dc_dmub_srv_fams2_update_config()
1714 for (i = 0; i < context->bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) { in dc_dmub_srv_fams2_update_config()
1724 &context->bw_ctx.bw.dcn.fams2_stream_params[i], in dc_dmub_srv_fams2_update_config()
1733 if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) { in dc_dmub_srv_fams2_update_config()
1736 …cmd[context->bw_ctx.bw.dcn.fams2_global_config.num_streams].fams2_config.header.multi_cmd_pending … in dc_dmub_srv_fams2_update_config()
1737 num_cmds += context->bw_ctx.bw.dcn.fams2_global_config.num_streams; in dc_dmub_srv_fams2_update_config()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
Ddcn201_clk_mgr.c89 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn201_update_clocks()

12