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/linux-6.12.1/arch/riscv/kernel/
Dtraps_misaligned.c319 ulong data_ulong; member
425 SET_RD(insn, regs, val.data_ulong << shift >> shift); in handle_misaligned_load()
429 set_f32_rd(insn, regs, val.data_ulong); in handle_misaligned_load()
457 val.data_ulong = GET_RS2(insn, regs); in handle_misaligned_store()
472 val.data_ulong = GET_F32_RS2(insn, regs); in handle_misaligned_store()
478 val.data_ulong = GET_RS2S(insn, regs); in handle_misaligned_store()
481 val.data_ulong = GET_RS2C(insn, regs); in handle_misaligned_store()
485 val.data_ulong = GET_RS2S(insn, regs); in handle_misaligned_store()
488 val.data_ulong = GET_RS2C(insn, regs); in handle_misaligned_store()
501 val.data_ulong = GET_F32_RS2S(insn, regs); in handle_misaligned_store()
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