Home
last modified time | relevance | path

Searched refs:csio_rd_reg32 (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/scsi/csiostor/
Dcsio_hw_t5.c62 csio_rd_reg32(hw, in csio_t5_set_mem_win()
158 if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST_F) in csio_t5_mc_read()
173 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i))); in csio_t5_mc_read()
213 if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST_F) in csio_t5_edc_read()
228 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i))); in csio_t5_edc_read()
272 edc_size = EDRAM0_SIZE_G(csio_rd_reg32(hw, MA_EDRAM0_BAR_A)); in csio_t5_memory_rw()
276 mc_size = EXT_MEM_SIZE_G(csio_rd_reg32(hw, in csio_t5_memory_rw()
293 mem_reg = csio_rd_reg32(hw, in csio_t5_memory_rw()
319 csio_rd_reg32(hw, in csio_t5_memory_rw()
324 *buf++ = csio_rd_reg32(hw, mem_base + offset); in csio_t5_memory_rw()
[all …]
Dcsio_hw.c138 val = csio_rd_reg32(hw, reg); in csio_hw_wait_op_done_val()
167 val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask; in csio_hw_tp_wr_bits_indirect()
175 uint32_t val = csio_rd_reg32(hw, reg) & ~mask; in csio_set_reg_field()
179 csio_rd_reg32(hw, reg); in csio_set_reg_field()
399 if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F) in csio_hw_sf1_read()
407 *valp = csio_rd_reg32(hw, SF_DATA_A); in csio_hw_sf1_read()
429 if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F) in csio_hw_sf1_write()
888 while (((reg = csio_rd_reg32(hw, PL_WHOAMI_A)) == 0xFFFFFFFF) && in csio_hw_dev_ready()
991 pcie_fw = csio_rd_reg32(hw, PCIE_FW_A); in csio_do_hello()
1290 if (!(csio_rd_reg32(hw, PCIE_FW_A) & PCIE_FW_HALT_F)) in csio_hw_fw_restart()
[all …]
Dcsio_mb.c1113 csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A)); in csio_mb_intr_enable()
1127 csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A)); in csio_mb_intr_disable()
1176 csio_rd_reg32(hw, ctl_reg); in csio_mb_debug_cmd_handler()
1233 owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg)); in csio_mb_issue()
1238 owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg)); in csio_mb_issue()
1287 csio_rd_reg32(hw, ctl_reg); in csio_mb_issue()
1302 ctl = csio_rd_reg32(hw, ctl_reg); in csio_mb_issue()
1485 pl_cause = csio_rd_reg32(hw, MYPF_REG(PL_PF_INT_CAUSE_A)); in csio_mb_isr_handler()
1486 cim_cause = csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A)); in csio_mb_isr_handler()
1502 ctl = csio_rd_reg32(hw, ctl_reg); in csio_mb_isr_handler()
[all …]
Dcsio_wr.c60 sge->sge_fl_buf_size[reg] = csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE0_A + in csio_get_flbuf_size()
1409 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2_A) + in csio_wr_fixup_host_params()
1413 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3_A) + in csio_wr_fixup_host_params()
1463 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A); in csio_wr_get_sge()
1489 timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1_A); in csio_wr_get_sge()
1490 timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3_A); in csio_wr_get_sge()
1491 timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5_A); in csio_wr_get_sge()
1506 ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD_A); in csio_wr_get_sge()
1535 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A); in csio_wr_set_sge()
Dcsio_hw.h563 #define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r))) macro
Dcsio_init.c127 i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A); in csio_setup_debugfs()