| /linux-6.12.1/sound/pci/ice1712/ |
| D | ak4xxx.c | 56 if (priv->cs_mask == priv->cs_addr) { in snd_ice1712_akm4xxx_write()
58 tmp |= priv->cs_mask; /* start without chip select */ in snd_ice1712_akm4xxx_write()
60 tmp &= ~priv->cs_mask; /* chip select low */ in snd_ice1712_akm4xxx_write()
66 tmp &= ~priv->cs_mask; in snd_ice1712_akm4xxx_write()
93 if (priv->cs_mask == priv->cs_addr) { in snd_ice1712_akm4xxx_write()
96 tmp &= ~priv->cs_mask; in snd_ice1712_akm4xxx_write()
100 tmp |= priv->cs_mask; /* chip select high to trigger */ in snd_ice1712_akm4xxx_write()
102 tmp &= ~priv->cs_mask; in snd_ice1712_akm4xxx_write()
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| D | delta.c | 253 priv->cs_mask = in delta_ak4524_lock()
267 priv->cs_mask = ICE1712_DELTA_1010LT_CS; in delta1010lt_ak4524_lock()
280 priv->cs_mask = in delta66e_ak4524_lock()
294 priv->cs_mask = in vx442_ak4524_lock()
448 .cs_mask = ICE1712_DELTA_AP_CS_CODEC,
469 .cs_mask = ICE1712_DELTA_AP_CS_CODEC,
491 .cs_mask = 0,
513 .cs_mask = 0,
536 .cs_mask = 0,
558 .cs_mask = 0,
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| D | revo.c | 238 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1 | VT1724_REVO_CS2,
260 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1 | VT1724_REVO_CS2,
281 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1,
299 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS1,
349 .cs_mask = VT1724_REVO_CS0 | VT1724_REVO_CS3,
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| D | ews.c | 205 tmp = priv->cs_mask = priv->cs_addr = (1 << chip) & ICE1712_6FIRE_AK4524_CS_MASK; in dmx6fire_ak4524_lock()
348 .cs_mask = 0,
369 .cs_mask = ICE1712_EWX2496_AK4524_CS,
390 .cs_mask = 0,
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| D | hoontech.c | 292 .cs_mask = ICE1712_STDSP24_AK4524_CS, in snd_ice1712_value_init()
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| D | ice1712.h | 256 unsigned int cs_mask; /* bit mask for select/deselect address */ member
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.c | 54 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
834 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE) in dce112_program_pixel_clk_resync()
996 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) in dcn31_program_pix_clk()
1010 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) in dcn31_program_pix_clk()
1347 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) in dcn3_program_pix_clk()
1671 const struct dce110_clk_src_mask *cs_mask) in dce110_clk_src_construct() argument
1683 clk_src->cs_mask = cs_mask; in dce110_clk_src_construct()
1696 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; in dce110_clk_src_construct()
1698 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; in dce110_clk_src_construct()
1715 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; in dce110_clk_src_construct()
[all …]
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| D | dce_clock_source.h | 236 const struct dce110_clk_src_mask *cs_mask; member
263 const struct dce110_clk_src_mask *cs_mask);
272 const struct dce110_clk_src_mask *cs_mask);
281 const struct dce110_clk_src_mask *cs_mask);
290 const struct dce110_clk_src_mask *cs_mask);
299 const struct dce110_clk_src_mask *cs_mask);
308 const struct dce110_clk_src_mask *cs_mask);
317 const struct dce110_clk_src_mask *cs_mask);
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| /linux-6.12.1/drivers/spi/ |
| D | spi-dln2.c | 132 static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask) in dln2_spi_cs_set() argument
146 tx.cs = ~cs_mask; in dln2_spi_cs_set()
162 static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable) in dln2_spi_cs_enable() argument
171 tx.cs = cs_mask; in dln2_spi_cs_enable()
179 u8 cs_mask = GENMASK(dln2->host->num_chipselect - 1, 0); in dln2_spi_cs_enable_all() local
181 return dln2_spi_cs_enable(dln2, cs_mask, enable); in dln2_spi_cs_enable_all()
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| /linux-6.12.1/drivers/usb/host/ |
| D | ehci-sched.c | 203 ps->usecs, ps->c_usecs, ps->cs_mask); in bandwidth_dbg()
239 if (qh->ps.cs_mask & m) in reserve_release_intr_bandwidth()
891 qh->ps.cs_mask = qh->ps.period ? in qh_schedule()
897 hw->hw_info2 |= cpu_to_hc32(ehci, qh->ps.cs_mask); in qh_schedule()
1093 stream->ps.cs_mask = 1; in iso_stream_init()
1097 stream->ps.cs_mask |= tmp << (8 + 2); in iso_stream_init()
1099 stream->ps.cs_mask = smask_out[hs_transfers - 1]; in iso_stream_init()
1330 s_mask = stream->ps.cs_mask; in reserve_release_iso_bandwidth()
1395 mask = stream->ps.cs_mask << (uframe & 7); in sitd_slot_ok()
1398 if (((stream->ps.cs_mask & 0xff) << (uframe & 7)) >= (1 << 7)) in sitd_slot_ok()
[all …]
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| D | ehci.h | 53 u16 cs_mask; /* C-mask and S-mask bytes */ member
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| /linux-6.12.1/arch/mips/include/asm/octeon/ |
| D | cvmx-lmcx-defs.h | 1625 uint64_t cs_mask:8; member
1627 uint64_t cs_mask:8;
1639 uint64_t cs_mask:8; member
1641 uint64_t cs_mask:8;
1986 uint64_t cs_mask:8; member
1988 uint64_t cs_mask:8;
2003 uint64_t cs_mask:8; member
2005 uint64_t cs_mask:8;
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| /linux-6.12.1/drivers/edac/ |
| D | amd64_edac.c | 2203 u64 cs_base, cs_mask; in f1x_lookup_addr_in_dct() local
2219 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); in f1x_lookup_addr_in_dct()
2222 csrow, cs_base, cs_mask); in f1x_lookup_addr_in_dct()
2224 cs_mask = ~cs_mask; in f1x_lookup_addr_in_dct()
2227 (in_addr & cs_mask), (cs_base & cs_mask)); in f1x_lookup_addr_in_dct()
2229 if ((in_addr & cs_mask) == (cs_base & cs_mask)) { in f1x_lookup_addr_in_dct()
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| /linux-6.12.1/drivers/pcmcia/ |
| D | tcic.c | 463 u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12)); in init_tcic() local
465 if ((cs_mask & (1 << i)) && in init_tcic()
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| D | i82365.c | 706 u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12)); in add_pcic() local
708 if ((cs_mask & (1 << cs_irq)) && in add_pcic()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce100/ |
| D | dce100_resource.c | 339 static const struct dce110_clk_src_mask cs_mask = { variable
740 regs, &cs_shift, &cs_mask)) { in dce100_clock_source_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce120/ |
| D | dce120_resource.c | 421 static const struct dce110_clk_src_mask cs_mask = { variable
546 regs, &cs_shift, &cs_mask)) { in dce120_clock_source_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| D | dcn201_resource.c | 319 static const struct dce110_clk_src_mask cs_mask = { variable
831 regs, &cs_shift, &cs_mask)) { in dcn201_clock_source_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| D | dce112_resource.c | 383 static const struct dce110_clk_src_mask cs_mask = { variable
761 regs, &cs_shift, &cs_mask)) { in dce112_clock_source_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 363 static const struct dce110_clk_src_mask cs_mask = { variable
766 regs, &cs_shift, &cs_mask)) { in dce60_clock_source_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| D | dce80_resource.c | 365 static const struct dce110_clk_src_mask cs_mask = { variable
772 regs, &cs_shift, &cs_mask)) { in dce80_clock_source_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| D | dcn314_resource.c | 240 static const struct dce110_clk_src_mask cs_mask = { variable
1658 regs, &cs_shift, &cs_mask)) { in dcn31_clock_source_create()
1797 regs, &cs_shift, &cs_mask)) { in dcn30_clock_source_create()
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| /linux-6.12.1/kernel/cgroup/ |
| D | cpuset.c | 4013 const struct cpumask *cs_mask; in cpuset_cpus_allowed_fallback() local
4017 cs_mask = task_cs(tsk)->cpus_allowed; in cpuset_cpus_allowed_fallback()
4018 if (is_in_v2_mode() && cpumask_subset(cs_mask, possible_mask)) { in cpuset_cpus_allowed_fallback()
4019 do_set_cpus_allowed(tsk, cs_mask); in cpuset_cpus_allowed_fallback()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| D | dcn31_resource.c | 231 static const struct dce110_clk_src_mask cs_mask = { variable
1602 regs, &cs_shift, &cs_mask)) { in dcn31_clock_source_create()
1862 regs, &cs_shift, &cs_mask)) { in dcn30_clock_source_create()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| D | dce110_resource.c | 375 static const struct dce110_clk_src_mask cs_mask = { variable
785 regs, &cs_shift, &cs_mask)) { in dce110_clock_source_create()
|