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Searched refs:cp_int_cntl_reg (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dgfx_v12_0.c1738 u32 tmp, cp_int_cntl_reg; in gfx_v12_0_enable_gui_idle_interrupt() local
1746 cp_int_cntl_reg = gfx_v12_0_get_cpg_int_cntl(adev, i, j); in gfx_v12_0_enable_gui_idle_interrupt()
1748 if (cp_int_cntl_reg) { in gfx_v12_0_enable_gui_idle_interrupt()
1749 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_enable_gui_idle_interrupt()
1758 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); in gfx_v12_0_enable_gui_idle_interrupt()
4641 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v12_0_set_gfx_eop_interrupt_state() local
4646 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v12_0_set_gfx_eop_interrupt_state()
4659 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_gfx_eop_interrupt_state()
4664 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v12_0_set_gfx_eop_interrupt_state()
4667 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v12_0_set_gfx_eop_interrupt_state()
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Dgfx_v11_0.c2025 u32 tmp, cp_int_cntl_reg; in gfx_v11_0_enable_gui_idle_interrupt() local
2033 cp_int_cntl_reg = gfx_v11_0_get_cpg_int_cntl(adev, i, j); in gfx_v11_0_enable_gui_idle_interrupt()
2035 if (cp_int_cntl_reg) { in gfx_v11_0_enable_gui_idle_interrupt()
2036 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_enable_gui_idle_interrupt()
2045 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); in gfx_v11_0_enable_gui_idle_interrupt()
6104 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v11_0_set_gfx_eop_interrupt_state() local
6109 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6112 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1); in gfx_v11_0_set_gfx_eop_interrupt_state()
6125 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v11_0_set_gfx_eop_interrupt_state()
6130 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v11_0_set_gfx_eop_interrupt_state()
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Dgfx_v10_0.c5267 u32 tmp, cp_int_cntl_reg; in gfx_v10_0_enable_gui_idle_interrupt() local
5275 cp_int_cntl_reg = gfx_v10_0_get_cpg_int_cntl(adev, i, j); in gfx_v10_0_enable_gui_idle_interrupt()
5277 if (cp_int_cntl_reg) { in gfx_v10_0_enable_gui_idle_interrupt()
5278 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_enable_gui_idle_interrupt()
5287 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp); in gfx_v10_0_enable_gui_idle_interrupt()
8962 uint32_t cp_int_cntl, cp_int_cntl_reg; in gfx_v10_0_set_gfx_eop_interrupt_state() local
8967 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); in gfx_v10_0_set_gfx_eop_interrupt_state()
8970 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); in gfx_v10_0_set_gfx_eop_interrupt_state()
8983 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v10_0_set_gfx_eop_interrupt_state()
8986 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v10_0_set_gfx_eop_interrupt_state()
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Dgfx_v9_0.c6039 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v9_0_set_priv_reg_fault_state() local
6051 cp_int_cntl_reg = gfx_v9_0_get_cpc_int_cntl(adev, i + 1, j); in gfx_v9_0_set_priv_reg_fault_state()
6053 if (cp_int_cntl_reg) { in gfx_v9_0_set_priv_reg_fault_state()
6054 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_set_priv_reg_fault_state()
6058 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_priv_reg_fault_state()
6075 u32 cp_int_cntl_reg, cp_int_cntl; in gfx_v9_0_set_bad_op_fault_state() local
6087 cp_int_cntl_reg = gfx_v9_0_get_cpc_int_cntl(adev, i + 1, j); in gfx_v9_0_set_bad_op_fault_state()
6089 if (cp_int_cntl_reg) { in gfx_v9_0_set_bad_op_fault_state()
6090 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); in gfx_v9_0_set_bad_op_fault_state()
6094 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); in gfx_v9_0_set_bad_op_fault_state()