Searched refs:cp_hqd_pq_base_hi (Results 1 – 22 of 22) sorted by relevance
193 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()353 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd_hiq()
194 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
177 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
185 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
231 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
252 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
88 uint32_t cp_hqd_pq_base_hi; member
297 uint32_t cp_hqd_pq_base_hi; member
307 uint32_t cp_hqd_pq_base_hi; member
812 uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89) member
813 uint32_t cp_hqd_pq_base_hi; member
1042 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in mes_v12_0_mqd_init()1139 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); in mes_v12_0_queue_init_register()
1076 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in mes_v11_0_mqd_init()1166 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); in mes_v11_0_queue_init_register()
1868 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v9_4_3_xcc_mqd_init()1980 mqd->cp_hqd_pq_base_hi); in gfx_v9_4_3_xcc_kiq_init_register()
3053 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v12_0_compute_mqd_init()3178 mqd->cp_hqd_pq_base_hi); in gfx_v12_0_kiq_init_register()
4108 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v11_0_compute_mqd_init()4234 mqd->cp_hqd_pq_base_hi); in gfx_v11_0_kiq_init_register()
3547 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v9_0_mqd_init()3658 mqd->cp_hqd_pq_base_hi); in gfx_v9_0_kiq_init_register()
2850 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v7_0_mqd_init()
6832 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v10_0_compute_mqd_init()6943 mqd->cp_hqd_pq_base_hi); in gfx_v10_0_kiq_init_register()
4456 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in gfx_v8_0_mqd_init()
4443 u32 cp_hqd_pq_base_hi; member4653 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in cik_cp_compute_resume()4655 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); in cik_cp_compute_resume()