Searched refs:control_status_reg (Results 1 – 2 of 2) sorted by relevance
51 u32 control_status_reg; in xilinx_wdt_start() local63 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_start()64 control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); in xilinx_wdt_start()66 iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK), in xilinx_wdt_start()80 u32 control_status_reg; in xilinx_wdt_stop() local85 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_stop()87 iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK), in xilinx_wdt_stop()103 u32 control_status_reg; in xilinx_wdt_keepalive() local108 control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); in xilinx_wdt_keepalive()109 control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); in xilinx_wdt_keepalive()[all …]
71 u32 control_status_reg; in xilinx_wwdt_start() local87 control_status_reg = ioread32(xdev->base + XWWDT_ESR_OFFSET); in xilinx_wwdt_start()88 control_status_reg |= XWWDT_ESR_WEN_MASK; in xilinx_wwdt_start()89 iowrite32(control_status_reg, xdev->base + XWWDT_ESR_OFFSET); in xilinx_wwdt_start()101 u32 control_status_reg; in xilinx_wwdt_keepalive() local109 control_status_reg = ioread32(xdev->base + XWWDT_ESR_OFFSET); in xilinx_wwdt_keepalive()110 control_status_reg |= XWWDT_ESR_WSW_MASK; in xilinx_wwdt_keepalive()111 iowrite32(control_status_reg, xdev->base + XWWDT_ESR_OFFSET); in xilinx_wwdt_keepalive()