| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_lib.c | 170 display_clocks_and_cfg_st *clks_cfg; in dml_log_pipe_params() local
179 clks_cfg = &(pipes[i].clks_cfg); in dml_log_pipe_params()
277 dml_print("DML PARAMS: voltage = %d\n", clks_cfg->voltage); in dml_log_pipe_params()
278 dml_print("DML PARAMS: dppclk_mhz = %3.2f\n", clks_cfg->dppclk_mhz); in dml_log_pipe_params()
279 dml_print("DML PARAMS: refclk_mhz = %3.2f\n", clks_cfg->refclk_mhz); in dml_log_pipe_params()
280 dml_print("DML PARAMS: dispclk_mhz = %3.2f\n", clks_cfg->dispclk_mhz); in dml_log_pipe_params()
281 dml_print("DML PARAMS: dcfclk_mhz = %3.2f\n", clks_cfg->dcfclk_mhz); in dml_log_pipe_params()
282 dml_print("DML PARAMS: socclk_mhz = %3.2f\n", clks_cfg->socclk_mhz); in dml_log_pipe_params()
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| D | display_mode_vba.c | 68 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0) in dml_get_voltage_level()
538 display_clocks_and_cfg_st *clks = &pipes[j].clks_cfg; in fetch_pipe_params()
1083 mode_lib->vba.VoltageLevel = mode_lib->vba.cache_pipes[0].clks_cfg.voltage; in ModeSupportAndSystemConfiguration()
1093 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz; in ModeSupportAndSystemConfiguration()
1094 mode_lib->vba.SOCCLK = mode_lib->vba.cache_pipes[0].clks_cfg.socclk_mhz; in ModeSupportAndSystemConfiguration()
1095 if (mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz > 0.0) in ModeSupportAndSystemConfiguration()
1096 mode_lib->vba.DISPCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dispclk_mhz; in ModeSupportAndSystemConfiguration()
1109 if (mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz > 0.0) in ModeSupportAndSystemConfiguration()
1110 mode_lib->vba.DPPCLK[k] = mode_lib->vba.cache_pipes[pipe_idx].clks_cfg.dppclk_mhz; in ModeSupportAndSystemConfiguration()
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| D | display_mode_structs.h | 560 display_clocks_and_cfg_st clks_cfg; member
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| D | dml1_display_rq_dlg_calc.c | 1018 double refclk_freq_in_mhz = e2e_pipe_param->clks_cfg.refclk_mhz; in dml1_rq_dlg_get_dlg_params()
1019 double dppclk_freq_in_mhz = e2e_pipe_param->clks_cfg.dppclk_mhz; in dml1_rq_dlg_get_dlg_params()
1020 double dispclk_freq_in_mhz = e2e_pipe_param->clks_cfg.dispclk_mhz; in dml1_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| D | dcn301_fpu.c | 303 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
457 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn301_fpu_calculate_wm_and_dlg()
458 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn301_fpu_calculate_wm_and_dlg()
461 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn301_fpu_calculate_wm_and_dlg()
462 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn301_fpu_calculate_wm_and_dlg()
464 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn301_fpu_calculate_wm_and_dlg()
465 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn301_fpu_calculate_wm_and_dlg()
466 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn301_fpu_calculate_wm_and_dlg()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 362 … dml->vba.WritebackAllowDRAMClockChangeEndPosition[cur_pipe] * pipes[0].clks_cfg.refclk_mhz; /* nu… in dcn30_fpu_set_mcif_arb_params()
428 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
429 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
430 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
438 pipes[0].clks_cfg.voltage = 1; in dcn30_fpu_calculate_wm_and_dlg()
439 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
454 pipes[0].clks_cfg.voltage = vlevel; in dcn30_fpu_calculate_wm_and_dlg()
455 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_fpu_calculate_wm_and_dlg()
557 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
558 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn30_fpu_calculate_wm_and_dlg()
[all …]
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| D | display_rq_dlg_calc_30.c | 906 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.c | 506 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
544 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
545 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn31_calculate_wm_and_dlg_fp()
548 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
549 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
551 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
552 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
553 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
[all …]
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| D | display_rq_dlg_calc_31.c | 868 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 1199 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn20_calculate_dlg_params()
1200 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn20_calculate_dlg_params()
1202 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn20_calculate_dlg_params()
1368 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn20_populate_dml_pipes_from_context()
1746 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn20_calculate_wm()
1747 …pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw… in dcn20_calculate_wm()
1750 pipes[pipe_cnt].clks_cfg.dppclk_mhz = in dcn20_calculate_wm()
1759 pipes[pipe_cnt].clks_cfg.dppclk_mhz = in dcn20_calculate_wm()
1769 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn20_calculate_wm()
1770 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn20_calculate_wm()
[all …]
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| D | display_rq_dlg_calc_20.c | 794 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_20v2.c | 794 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 506 pipes[0].clks_cfg.voltage = vlevel; in dcn32_set_phantom_stream_timing()
507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn32_set_phantom_stream_timing()
508 pipes[0].clks_cfg.socclk_mhz = socclk; in dcn32_set_phantom_stream_timing()
1521 pipes[0].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, *pipe_cnt, 0); in dcn32_full_validate_bw_helper()
1720 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn32_calculate_dlg_params()
1721 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn32_calculate_dlg_params()
1723 … context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn32_calculate_dlg_params()
2429 pipes[0].clks_cfg.voltage = vlevel_temp; in dcn32_calculate_wm_and_dlg_fpu()
2430 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn32_calculate_wm_and_dlg_fpu()
2431 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel_temp].socclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()
[all …]
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| D | display_rq_dlg_calc_32.c | 215 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml32_rq_dlg_get_dlg_reg()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| D | dcn_calcs.c | 494 input->clks_cfg.dcfclk_mhz = v->dcfclk; in dcn_bw_calc_rq_dlg_ttu()
495 input->clks_cfg.dispclk_mhz = v->dispclk; in dcn_bw_calc_rq_dlg_ttu()
496 input->clks_cfg.dppclk_mhz = v->dppclk; in dcn_bw_calc_rq_dlg_ttu()
497 input->clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0; in dcn_bw_calc_rq_dlg_ttu()
498 input->clks_cfg.socclk_mhz = v->socclk; in dcn_bw_calc_rq_dlg_ttu()
499 input->clks_cfg.voltage = v->voltage_level; in dcn_bw_calc_rq_dlg_ttu()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 840 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | display_rq_dlg_calc_314.c | 953 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
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