Home
last modified time | relevance | path

Searched refs:clk_sel (Results 1 – 25 of 27) sorted by relevance

12

/linux-6.12.1/drivers/gpu/drm/imx/ipuv3/
Dimx-ldb.c103 struct clk *clk_sel[4]; /* parent of display clock */ member
189 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); in imx_ldb_set_clock()
203 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) { in imx_ldb_encoder_enable()
211 clk_set_parent(ldb->clk_sel[mux], ldb->clk[0]); in imx_ldb_encoder_enable()
212 clk_set_parent(ldb->clk_sel[mux], ldb->clk[1]); in imx_ldb_encoder_enable()
217 clk_set_parent(ldb->clk_sel[mux], ldb->clk[imx_ldb_ch->chno]); in imx_ldb_encoder_enable()
266 if (mux < 0 || mux >= ARRAY_SIZE(ldb->clk_sel)) { in imx_ldb_encoder_atomic_mode_set()
356 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); in imx_ldb_encoder_disable()
659 imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname); in imx_ldb_probe()
660 if (IS_ERR(imx_ldb->clk_sel[i])) { in imx_ldb_probe()
[all …]
/linux-6.12.1/arch/mips/include/asm/octeon/
Dcvmx-gpio-defs.h53 uint64_t clk_sel:2; member
67 uint64_t clk_sel:2;
97 uint64_t clk_sel:2; member
111 uint64_t clk_sel:2;
360 uint64_t clk_sel:2; member
374 uint64_t clk_sel:2;
/linux-6.12.1/drivers/clk/sophgo/
Dclk-cv18xx-ip.c682 if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel)) in mmux_recalc_rate()
705 if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel)) in mmux_set_rate()
721 s8 clk_sel; in mmux_get_parent() local
726 if (cv1800_clk_checkbit(&mmux->common, &mmux->clk_sel)) in mmux_get_parent()
727 clk_sel = 0; in mmux_get_parent()
729 clk_sel = 1; in mmux_get_parent()
730 mux = &mmux->mux[clk_sel]; in mmux_get_parent()
734 return mmux->sel2parent[clk_sel][cv1800_clk_regfield_get(reg, mux)]; in mmux_get_parent()
743 s8 clk_sel = mmux->parent2sel[index]; in mmux_set_parent() local
745 if (index == 0 || clk_sel == -1) { in mmux_set_parent()
[all …]
Dclk-cv18xx-ip.h53 struct cv1800_clk_regbit clk_sel; member
220 .clk_sel = CV1800_CLK_BIT(_clk_sel_reg, \
/linux-6.12.1/drivers/net/ethernet/atheros/atl1c/
Datl1c_hw.c274 void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel) in atl1c_start_phy_polling() argument
282 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_start_phy_polling()
306 u16 clk_sel = MDIO_CTRL_CLK_25_4; in atl1c_read_phy_core() local
315 clk_sel = MDIO_CTRL_CLK_25_128; in atl1c_read_phy_core()
320 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_read_phy_core()
326 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_read_phy_core()
339 atl1c_start_phy_polling(hw, clk_sel); in atl1c_read_phy_core()
355 u16 clk_sel = MDIO_CTRL_CLK_25_4; in atl1c_write_phy_core() local
363 clk_sel = MDIO_CTRL_CLK_25_128; in atl1c_write_phy_core()
369 FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | in atl1c_write_phy_core()
[all …]
Datl1c_hw.h43 void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel);
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
Ddcn20_dccg.c83 uint32_t clk_sel = 0; in dccg2_get_dccg_ref_freq() local
85 REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel); in dccg2_get_dccg_ref_freq()
/linux-6.12.1/drivers/iio/adc/
Dvf610_adc.c103 enum clk_sel { enum
141 enum clk_sel clk_sel; member
238 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET; in vf610_adc_cfg_init()
258 switch (adc_feature->clk_sel) { in vf610_adc_cfg_post_set()
379 switch (adc_feature->clk_sel) { in vf610_adc_sample_set()
Dstm32-adc-core.c77 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); member
786 ret = priv->cfg->clk_sel(pdev, priv); in stm32_adc_probe()
857 .clk_sel = stm32f4_adc_clk_sel,
865 .clk_sel = stm32h7_adc_clk_sel,
874 .clk_sel = stm32h7_adc_clk_sel,
883 .clk_sel = stm32h7_adc_clk_sel,
Dad7173.c1029 unsigned int clk_sel) in ad7173_sel_clk() argument
1034 st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel); in ad7173_sel_clk()
1051 u32 clk_sel; in ad7173_clk_output_is_enabled() local
1053 clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode); in ad7173_clk_output_is_enabled()
1054 return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT; in ad7173_clk_output_is_enabled()
/linux-6.12.1/drivers/leds/rgb/
Dleds-qcom-lpg.c183 unsigned int clk_sel; member
422 unsigned int clk_sel, clk_len, best_clk = 0; in lpg_calc_freq() local
486 for (clk_sel = 1; clk_sel < clk_len; clk_sel++) { in lpg_calc_freq()
487 u64 numerator = period * clk_rate_arr[clk_sel]; in lpg_calc_freq()
504 clk_rate_arr[clk_sel]); in lpg_calc_freq()
510 best_clk = clk_sel; in lpg_calc_freq()
517 chan->clk_sel = best_clk; in lpg_calc_freq()
533 clk_rate = lpg_clk_rates_hi_res[chan->clk_sel]; in lpg_calc_duty()
536 clk_rate = lpg_clk_rates[chan->clk_sel]; in lpg_calc_duty()
553 val = chan->clk_sel; in lpg_apply_freq()
/linux-6.12.1/drivers/net/ethernet/atheros/alx/
Dhw.c64 u32 val, clk_sel; in alx_read_phy_core() local
70 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_read_phy_core()
81 clk_sel << ALX_MDIO_CLK_SEL_SHIFT; in alx_read_phy_core()
84 clk_sel << ALX_MDIO_CLK_SEL_SHIFT | in alx_read_phy_core()
101 u32 val, clk_sel; in alx_write_phy_core() local
104 clk_sel = hw->link_speed != SPEED_UNKNOWN ? in alx_write_phy_core()
114 clk_sel << ALX_MDIO_CLK_SEL_SHIFT | in alx_write_phy_core()
119 clk_sel << ALX_MDIO_CLK_SEL_SHIFT | in alx_write_phy_core()
/linux-6.12.1/drivers/gpio/
Dgpio-npcm-sgpio.c53 unsigned int *clk_sel; member
297 iowrite8(clk_cfg->clk_sel[i] | tmp, in npcm_sgpio_setup_clk()
588 .clk_sel = npcm750_CLK_SEL,
594 .clk_sel = npcm845_CLK_SEL,
/linux-6.12.1/drivers/tty/serial/
Dsamsung_tty.c1357 static void s3c24xx_serial_setsource(struct uart_port *port, u8 clk_sel) in s3c24xx_serial_setsource() argument
1366 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel) in s3c24xx_serial_setsource()
1370 ucon |= clk_sel << info->clksel_shift; in s3c24xx_serial_setsource()
1388 if (ourport->cfg->clk_sel && in s3c24xx_serial_getclk()
1389 !(ourport->cfg->clk_sel & (1 << cnt))) in s3c24xx_serial_getclk()
1480 u8 clk_sel = 0; in s3c24xx_serial_set_termios() local
1493 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); in s3c24xx_serial_set_termios()
1504 s3c24xx_serial_setsource(port, clk_sel); in s3c24xx_serial_set_termios()
1783 u8 clk_sel, clk_num; in s3c24xx_serial_enable_baudclk() local
1785 clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel; in s3c24xx_serial_enable_baudclk()
[all …]
/linux-6.12.1/sound/soc/sti/
Duniperif_player.c957 if (player->clk_sel) { in uni_player_resume()
958 ret = regmap_field_write(player->clk_sel, 1); in uni_player_resume()
1031 player->clk_sel = regmap_field_alloc(regmap, regfield[0]); in uni_player_parse_dt_audio_glue()
1083 if (player->clk_sel) { in uni_player_init()
1084 ret = regmap_field_write(player->clk_sel, 1); in uni_player_init()
Duniperif.h1300 struct regmap_field *clk_sel; member
/linux-6.12.1/drivers/video/fbdev/
Dgrvga.c42 int clk_sel; member
112 par->clk_sel = i; in grvga_check_var()
180 __raw_writel((par->clk_sel << 6) | (func << 4) | 1, in grvga_set_par()
/linux-6.12.1/drivers/clk/ralink/
Dclk-mt7621.c261 u32 clkcfg, clk_sel, curclk, ffiv, ffrac; in mt7621_cpu_recalc_rate() local
266 clk_sel = FIELD_GET(CPU_CLK_SEL_MASK, clkcfg); in mt7621_cpu_recalc_rate()
272 switch (clk_sel) { in mt7621_cpu_recalc_rate()
/linux-6.12.1/drivers/clk/imx/
Dclk-imx93.c18 enum clk_sel { enum
54 enum clk_sel sel;
/linux-6.12.1/drivers/spi/
Dspi-sunplus-sp7021.c287 u32 clk_rate, clk_sel, div; in sp7021_spi_setup_clk() local
292 clk_sel = (div / 2) - 1; in sp7021_spi_setup_clk()
294 pspim->xfer_conf |= FIELD_PREP(SP7021_CLK_MASK, clk_sel); in sp7021_spi_setup_clk()
Dspi-geni-qcom.c361 u32 clk_sel, m_clk_cfg, idx, div; in geni_spi_set_clock_and_bw() local
383 clk_sel = idx & CLK_SEL_MSK; in geni_spi_set_clock_and_bw()
385 writel(clk_sel, se->base + SE_GENI_CLK_SEL); in geni_spi_set_clock_and_bw()
/linux-6.12.1/include/linux/
Dserial_s3c.h288 unsigned int clk_sel; member
/linux-6.12.1/drivers/clk/mvebu/
Darmada-37xx-periph.c67 u32 clk_sel; member
702 data->clk_sel = readl(data->reg + CLK_SEL); in armada_3700_periph_clock_suspend()
718 writel(data->clk_sel, data->reg + CLK_SEL); in armada_3700_periph_clock_resume()
/linux-6.12.1/sound/soc/intel/atom/sst/
Dsst.h117 u64 clk_sel:3; member
/linux-6.12.1/drivers/media/dvb-frontends/
Dstv0900_core.c287 u32 m_div, clk_sel; in stv0900_set_mclk() local
298 clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6); in stv0900_set_mclk()
299 m_div = ((clk_sel * mclk) / intp->quartz) - 1; in stv0900_set_mclk()

12