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Searched refs:clk_rate_hz (Results 1 – 2 of 2) sorted by relevance

/linux-6.12.1/drivers/pwm/
Dpwm-axi-pwmgen.c46 unsigned long clk_rate_hz; member
69 period_cnt = mul_u64_u64_div_u64(state->period, ddata->clk_rate_hz, NSEC_PER_SEC); in axi_pwmgen_apply()
80 duty_cnt = mul_u64_u64_div_u64(state->duty_cycle, ddata->clk_rate_hz, NSEC_PER_SEC); in axi_pwmgen_apply()
115 state->period = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz); in axi_pwmgen_get_state()
121 state->duty_cycle = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz); in axi_pwmgen_get_state()
208 ddata->clk_rate_hz = clk_get_rate(clk); in axi_pwmgen_probe()
209 if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC) in axi_pwmgen_probe()
211 "Invalid clock rate: %lu\n", ddata->clk_rate_hz); in axi_pwmgen_probe()
/linux-6.12.1/drivers/i2c/busses/
Di2c-hisi.c463 u64 clk_rate_hz; in hisi_i2c_probe() local
489 ret = device_property_read_u64(dev, "clk_rate", &clk_rate_hz); in hisi_i2c_probe()
493 clk_rate_hz = clk_get_rate(ctlr->clk); in hisi_i2c_probe()
496 ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); in hisi_i2c_probe()