| /linux-6.12.1/drivers/clk/mxs/ |
| D | clk-pll.c | 23 struct clk_pll { struct
30 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
34 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare()
45 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare()
52 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable()
61 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable()
69 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
85 struct clk_pll *pll; in mxs_clk_pll()
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| /linux-6.12.1/arch/m68k/coldfire/ |
| D | m523x.c | 32 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
34 CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
35 CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
36 CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
37 CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
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| D | m528x.c | 34 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
36 CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
37 CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
38 CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
39 CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
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| D | m527x.c | 33 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
35 CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
36 CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
37 CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
38 CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
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| D | m5407.c | 29 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
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| D | m5206.c | 29 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
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| D | m5307.c | 38 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
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| D | m54xx.c | 38 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
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| D | m525x.c | 29 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
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| D | m5272.c | 40 CLKDEV_INIT(NULL, "pll.0", &clk_pll),
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| /linux-6.12.1/drivers/clk/qcom/ |
| D | clk-pll.c | 26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable()
67 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_disable()
82 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
128 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_determine_rate()
143 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate()
179 static int wait_for_pll(struct clk_pll *pll) in wait_for_pll()
203 struct clk_pll *p = to_clk_pll(clk_hw_get_parent(hw)); in clk_pll_vote_enable()
218 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap, in clk_pll_configure()
245 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap, in clk_pll_configure_sr()
254 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, in clk_pll_configure_sr_hpm_lp()
[all …]
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| D | clk-pll.h | 39 struct clk_pll { struct
59 #define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr) argument
76 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
78 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
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| /linux-6.12.1/drivers/clk/at91/ |
| D | clk-pll.c | 32 #define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
34 struct clk_pll { struct
57 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() argument
100 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_is_prepared()
107 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare()
116 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
124 static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate, in clk_pll_get_best_div_mul()
237 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_round_rate()
246 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate()
266 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_save_context()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | moxa,moxart-clock.txt | 37 clk_pll: clk_pll@98100000 {
47 clocks = <&clk_pll>;
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| /linux-6.12.1/sound/soc/amd/acp/ |
| D | acp63.c | 164 union clk_pll_req_no clk_pll; in acp63_i2s_master_clock_generate() local
172 clk_pll.bits.fb_mult_int = 0x31; in acp63_i2s_master_clock_generate()
173 clk_pll.bits.pll_spine_div = 0; in acp63_i2s_master_clock_generate()
174 clk_pll.bits.gb_mult_frac = 0x26E9; in acp63_i2s_master_clock_generate()
183 smn_write(smn_dev, CLK_PLL_REQ_N0, clk_pll.clk_pll_req_no_reg); in acp63_i2s_master_clock_generate()
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| /linux-6.12.1/drivers/clk/ |
| D | clk-nomadik.c | 145 struct clk_pll { struct
164 #define to_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
169 struct clk_pll *pll = to_pll(hw); in pll_clk_enable()
189 struct clk_pll *pll = to_pll(hw); in pll_clk_disable()
208 struct clk_pll *pll = to_pll(hw); in pll_clk_is_enabled()
224 struct clk_pll *pll = to_pll(hw); in pll_clk_recalc_rate()
264 struct clk_pll *pll; in pll_clk_register()
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| D | clk-versaclock3.c | 677 static struct vc3_hw_data clk_pll[] = { variable
736 { .hw = &clk_pll[VC3_PLL1].hw },
740 { .hw = &clk_pll[VC3_PLL2].hw },
741 { .hw = &clk_pll[VC3_PLL3].hw }
744 { .hw = &clk_pll[VC3_PLL2].hw },
822 &clk_pll[VC3_PLL1].hw
876 &clk_pll[VC3_PLL3].hw
1033 for (i = 0; i < ARRAY_SIZE(clk_pll); i++) { in vc3_probe()
1034 clk_pll[i].regmap = regmap; in vc3_probe()
1035 ret = devm_clk_hw_register(dev, &clk_pll[i].hw); in vc3_probe()
[all …]
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| D | clk-vt8500.c | 41 struct clk_pll { struct
308 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
549 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_set_rate()
600 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_round_rate()
639 struct clk_pll *pll = to_clk_pll(hw); in vtwm_pll_recalc_rate()
677 struct clk_pll *pll_clk; in vtwm_pll_clk_init()
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| /linux-6.12.1/drivers/clk/spear/ |
| D | clk-vco-pll.c | 63 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
84 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_round_rate_index()
124 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_recalc_rate()
144 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_set_rate()
280 struct clk_pll *pll; in clk_register_vco_pll()
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| /linux-6.12.1/drivers/clk/keystone/ |
| D | pll.c | 68 struct clk_pll { struct
73 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) argument
78 struct clk_pll *pll = to_clk_pll(hw); in clk_pllclk_recalc()
126 struct clk_pll *pll; in clk_register_pll()
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| /linux-6.12.1/arch/arm/boot/dts/moxa/ |
| D | moxart.dtsi | 47 clk_pll: clk_pll@98100000 { label
57 clocks = <&clk_pll>;
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| /linux-6.12.1/drivers/gpu/drm/imx/ipuv3/ |
| D | imx-ldb.c | 105 struct clk *clk_pll[2]; /* upstream clock we can adjust */ member
174 clk_get_rate(ldb->clk_pll[chno]), serial_clk); in imx_ldb_set_clock()
175 clk_set_rate(ldb->clk_pll[chno], serial_clk); in imx_ldb_set_clock()
178 clk_get_rate(ldb->clk_pll[chno])); in imx_ldb_set_clock()
430 ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname); in imx_ldb_get_clk()
432 return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]); in imx_ldb_get_clk()
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| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-pllfh.h | 58 struct mtk_clk_pll clk_pll; member
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| D | clk-pllfh.c | 24 return container_of(pll, struct mtk_fh, clk_pll); in to_mtk_fh()
169 hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, in mtk_clk_register_pllfh()
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| /linux-6.12.1/drivers/staging/most/dim2/ |
| D | dim2.c | 92 struct clk *clk_pll; member
939 dev->clk_pll = devm_clk_get(&pdev->dev, "pll8_mlb"); in fsl_mx6_enable()
940 if (IS_ERR_OR_NULL(dev->clk_pll)) { in fsl_mx6_enable()
947 clk_prepare_enable(dev->clk_pll); in fsl_mx6_enable()
958 clk_disable_unprepare(dev->clk_pll); in fsl_mx6_disable()
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