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Searched refs:cfgBIFPLR0_PCIE_PORT_VC_CAP_REG2 (Results 1 – 2 of 2) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_7_7_0_offset.h1753 #define cfgBIFPLR0_PCIE_PORT_VC_CAP_REG2 … macro
Dnbio_7_2_0_offset.h2150 #define cfgBIFPLR0_PCIE_PORT_VC_CAP_REG2 … macro