| /linux-6.12.1/drivers/phy/ |
| D | phy-core-mipi-dphy.c | 24 struct phy_configure_opts_mipi_dphy *cfg) in phy_mipi_dphy_calc_config() argument
28 if (!cfg) in phy_mipi_dphy_calc_config()
39 cfg->clk_miss = 0; in phy_mipi_dphy_calc_config()
40 cfg->clk_post = 60000 + 52 * ui; in phy_mipi_dphy_calc_config()
41 cfg->clk_pre = 8; in phy_mipi_dphy_calc_config()
42 cfg->clk_prepare = 38000; in phy_mipi_dphy_calc_config()
43 cfg->clk_settle = 95000; in phy_mipi_dphy_calc_config()
44 cfg->clk_term_en = 0; in phy_mipi_dphy_calc_config()
45 cfg->clk_trail = 60000; in phy_mipi_dphy_calc_config()
46 cfg->clk_zero = 262000; in phy_mipi_dphy_calc_config()
[all …]
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| /linux-6.12.1/drivers/media/platform/samsung/exynos-gsc/ |
| D | gsc-regs.c | 22 u32 cfg; in gsc_wait_reset() local
25 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
26 if (!cfg) in gsc_wait_reset()
36 u32 cfg; in gsc_hw_set_frm_done_irq_mask() local
38 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
40 cfg |= GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
42 cfg &= ~GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
43 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
48 u32 cfg; in gsc_hw_set_gsc_irq_enable() local
50 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_gsc_irq_enable()
[all …]
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| /linux-6.12.1/drivers/media/platform/samsung/exynos4-is/ |
| D | fimc-reg.c | 21 u32 cfg; in fimc_hw_reset() local
23 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
24 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
25 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
28 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
29 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL); in fimc_hw_reset()
30 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
33 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
34 cfg &= ~FIMC_REG_CIGCTRL_SWRST; in fimc_hw_reset()
35 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
[all …]
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| D | fimc-lite-reg.c | 23 u32 cfg; in flite_hw_reset() local
25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
26 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; in flite_hw_reset()
27 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
30 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
31 if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY) in flite_hw_reset()
36 cfg |= FLITE_REG_CIGCTRL_SWRST; in flite_hw_reset()
37 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
42 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq() local
43 cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM; in flite_hw_clear_pending_irq()
[all …]
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| /linux-6.12.1/drivers/net/ethernet/marvell/octeon_ep/ |
| D | octep_config.h | 60 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
61 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
62 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
63 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
64 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
67 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
68 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) argument
69 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) argument
70 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt) argument
[all …]
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| /linux-6.12.1/drivers/media/platform/samsung/s3c-camif/ |
| D | camif-regs.c | 18 u32 cfg; in camif_hw_reset() local
20 cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT); in camif_hw_reset()
21 cfg |= CISRCFMT_ITU601_8BIT; in camif_hw_reset()
22 camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg); in camif_hw_reset()
25 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
26 cfg |= CIGCTRL_SWRST; in camif_hw_reset()
28 cfg |= CIGCTRL_IRQ_LEVEL; in camif_hw_reset()
29 camif_write(camif, S3C_CAMIF_REG_CIGCTRL, cfg); in camif_hw_reset()
32 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
33 cfg &= ~CIGCTRL_SWRST; in camif_hw_reset()
[all …]
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| /linux-6.12.1/drivers/net/ethernet/cavium/liquidio/ |
| D | octeon_config.h | 121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) argument
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) argument
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) argument
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) argument
129 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val argument
131 #define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs) argument
132 #define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr) argument
[all …]
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| /linux-6.12.1/drivers/pci/ |
| D | ecam.c | 32 struct pci_config_window *cfg; in pci_ecam_create() local
40 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); in pci_ecam_create()
41 if (!cfg) in pci_ecam_create()
48 cfg->parent = dev; in pci_ecam_create()
49 cfg->ops = ops; in pci_ecam_create()
50 cfg->busr.start = busr->start; in pci_ecam_create()
51 cfg->busr.end = busr->end; in pci_ecam_create()
52 cfg->busr.flags = IORESOURCE_BUS; in pci_ecam_create()
53 cfg->bus_shift = bus_shift; in pci_ecam_create()
54 bus_range = resource_size(&cfg->busr); in pci_ecam_create()
[all …]
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| /linux-6.12.1/sound/pci/hda/ |
| D | hda_auto_parser.c | 56 static void add_auto_cfg_input_pin(struct hda_codec *codec, struct auto_pin_cfg *cfg, in add_auto_cfg_input_pin() argument
59 if (cfg->num_inputs < AUTO_CFG_MAX_INS) { in add_auto_cfg_input_pin()
60 cfg->inputs[cfg->num_inputs].pin = nid; in add_auto_cfg_input_pin()
61 cfg->inputs[cfg->num_inputs].type = type; in add_auto_cfg_input_pin()
62 cfg->inputs[cfg->num_inputs].has_boost_on_pin = in add_auto_cfg_input_pin()
64 cfg->num_inputs++; in add_auto_cfg_input_pin()
169 struct auto_pin_cfg *cfg, in snd_hda_parse_pin_defcfg() argument
175 struct auto_out_pin line_out[ARRAY_SIZE(cfg->line_out_pins)]; in snd_hda_parse_pin_defcfg()
176 struct auto_out_pin speaker_out[ARRAY_SIZE(cfg->speaker_pins)]; in snd_hda_parse_pin_defcfg()
177 struct auto_out_pin hp_out[ARRAY_SIZE(cfg->hp_pins)]; in snd_hda_parse_pin_defcfg()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_phy_8998.c | 284 struct hdmi_8998_phy_pll_reg_cfg *cfg) in pll_calculate() argument
331 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
333 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
335 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
336 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
337 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
338 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
339 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
340 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
341 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
[all …]
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| D | hdmi_phy_8996.c | 219 struct hdmi_8996_phy_pll_reg_cfg *cfg) in pll_calculate() argument
286 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
288 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
290 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
291 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
292 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
293 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
294 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
295 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
296 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
[all …]
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| /linux-6.12.1/arch/x86/pci/ |
| D | mmconfig-shared.c | 37 static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) in pci_mmconfig_remove() argument
39 if (cfg->res.parent) in pci_mmconfig_remove()
40 release_resource(&cfg->res); in pci_mmconfig_remove()
41 list_del(&cfg->list); in pci_mmconfig_remove()
42 kfree(cfg); in pci_mmconfig_remove()
47 struct pci_mmcfg_region *cfg, *tmp; in free_all_mmcfg() local
50 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list) in free_all_mmcfg()
51 pci_mmconfig_remove(cfg); in free_all_mmcfg()
56 struct pci_mmcfg_region *cfg; in list_add_sorted() local
59 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held()) { in list_add_sorted()
[all …]
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| D | mmconfig_64.c | 21 struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); in pci_dev_base() local
23 if (cfg && cfg->virt) in pci_dev_base()
24 return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12)); in pci_dev_base()
99 static void __iomem *mcfg_ioremap(struct pci_mmcfg_region *cfg) in mcfg_ioremap() argument
105 start = cfg->address + PCI_MMCFG_BUS_OFFSET(cfg->start_bus); in mcfg_ioremap()
106 num_buses = cfg->end_bus - cfg->start_bus + 1; in mcfg_ioremap()
110 addr -= PCI_MMCFG_BUS_OFFSET(cfg->start_bus); in mcfg_ioremap()
114 int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg) in pci_mmcfg_arch_map() argument
116 cfg->virt = mcfg_ioremap(cfg); in pci_mmcfg_arch_map()
117 if (!cfg->virt) { in pci_mmcfg_arch_map()
[all …]
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| /linux-6.12.1/drivers/net/ethernet/marvell/octeon_ep_vf/ |
| D | octep_vf_config.h | 56 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
57 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs) argument
58 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
59 #define CFG_GET_IQ_INSTR_SIZE(cfg) (64) argument
60 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
61 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold) argument
63 #define CFG_GET_OQ_NUM_DESC(cfg) ((cfg)->oq.num_descs) argument
64 #define CFG_GET_OQ_BUF_SIZE(cfg) ((cfg)->oq.buf_size) argument
65 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold) argument
66 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt) argument
[all …]
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| /linux-6.12.1/drivers/net/ethernet/marvell/octeontx2/af/ |
| D | rpm.c | 129 u64 cfg, last; in rpm_lmac_tx_enable() local
134 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_tx_enable()
135 last = cfg; in rpm_lmac_tx_enable()
137 cfg |= RPM_TX_EN; in rpm_lmac_tx_enable()
139 cfg &= ~(RPM_TX_EN); in rpm_lmac_tx_enable()
141 if (cfg != last) in rpm_lmac_tx_enable()
142 rpm_write(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG, cfg); in rpm_lmac_tx_enable()
149 u64 cfg; in rpm_lmac_rx_tx_enable() local
154 cfg = rpm_read(rpm, lmac_id, RPMX_MTI_MAC100X_COMMAND_CONFIG); in rpm_lmac_rx_tx_enable()
156 cfg |= RPM_RX_EN | RPM_TX_EN; in rpm_lmac_rx_tx_enable()
[all …]
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| /linux-6.12.1/tools/testing/selftests/drivers/net/hw/ |
| D | csum.py | 12 def test_receive(cfg, ipv4=False, extra_args=None): argument
14 if not cfg.have_rx_csum:
27 cmd(tx_cmd, host=cfg.remote)
30 def test_transmit(cfg, ipv4=False, extra_args=None): argument
32 if (not cfg.have_tx_csum_generic and
33 not (cfg.have_tx_csum_ipv4 and ipv4) and
34 not (cfg.have_tx_csum_ipv6 and not ipv4)):
49 with bkg(rx_cmd, host=cfg.remote, exit_wait=True):
50 wait_port_listen(34000, proto="udp", host=cfg.remote)
54 def test_builder(name, cfg, ipv4=False, tx=False, extra_args=""): argument
[all …]
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| D | rss_ctx.py | 22 def _rss_key_check(cfg, data=None, context=0): argument
24 data = get_rss(cfg, context=context)
31 def get_rss(cfg, context=0): argument
35 def get_drop_err_sum(cfg): argument
36 stats = ip("-s -s link show dev " + cfg.ifname, json=True)[0]
45 def ethtool_create(cfg, act, opts): argument
52 def require_ntuple(cfg): argument
62 def _get_rx_cnts(cfg, prev=None): argument
63 cfg.wait_hw_stats_settle()
64 data = cfg.netdevnl.qstats_get({"ifindex": cfg.ifindex, "scope": ["queue"]}, dump=True)
[all …]
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| /linux-6.12.1/drivers/gpu/drm/exynos/ |
| D | exynos_drm_gsc.c | 66 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) argument
381 u32 cfg; in gsc_sw_reset() local
385 cfg = (GSC_SW_RESET_SRESET); in gsc_sw_reset()
386 gsc_write(cfg, GSC_SW_RESET); in gsc_sw_reset()
390 cfg = gsc_read(GSC_SW_RESET); in gsc_sw_reset()
391 if (!cfg) in gsc_sw_reset()
396 if (cfg) { in gsc_sw_reset()
402 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); in gsc_sw_reset()
403 cfg |= (GSC_IN_BASE_ADDR_MASK | in gsc_sw_reset()
405 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); in gsc_sw_reset()
[all …]
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| D | exynos_drm_fimc.c | 139 u32 cfg; in fimc_sw_reset() local
142 cfg = fimc_read(ctx, EXYNOS_CISTATUS); in fimc_sw_reset()
143 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) in fimc_sw_reset()
164 u32 cfg; in fimc_set_type_ctrl() local
166 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
167 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | in fimc_set_type_ctrl()
174 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | in fimc_set_type_ctrl()
179 fimc_write(ctx, cfg, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
184 u32 cfg; in fimc_handle_jpeg() local
188 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_handle_jpeg()
[all …]
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| /linux-6.12.1/drivers/scsi/cxlflash/ |
| D | main.c | 50 struct cxlflash_cfg *cfg = afu->parent; in process_cmd_err() local
51 struct device *dev = &cfg->dev->dev; in process_cmd_err()
162 struct cxlflash_cfg *cfg = afu->parent; in cmd_complete() local
163 struct device *dev = &cfg->dev->dev; in cmd_complete()
181 spin_lock_irqsave(&cfg->tmf_slock, lock_flags); in cmd_complete()
182 cfg->tmf_active = false; in cmd_complete()
183 wake_up_all_locked(&cfg->tmf_waitq); in cmd_complete()
184 spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags); in cmd_complete()
198 struct cxlflash_cfg *cfg = hwq->afu->parent; in flush_pending_cmds() local
218 spin_lock_irqsave(&cfg->tmf_slock, lock_flags); in flush_pending_cmds()
[all …]
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| /linux-6.12.1/tools/testing/selftests/bpf/prog_tests/ |
| D | core_extern.c | 25 const char *cfg; member
32 .cfg = "CONFIG_BPF_SYSCALL=n\n"
54 { .name = "tristate (y)", .cfg = CFG"CONFIG_TRISTATE=y\n",
56 { .name = "tristate (n)", .cfg = CFG"CONFIG_TRISTATE=n\n",
58 { .name = "tristate (m)", .cfg = CFG"CONFIG_TRISTATE=m\n",
60 { .name = "tristate (int)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=1" },
61 { .name = "tristate (bad)", .fails = 1, .cfg = CFG"CONFIG_TRISTATE=M" },
63 { .name = "bool (y)", .cfg = CFG"CONFIG_BOOL=y\n",
65 { .name = "bool (n)", .cfg = CFG"CONFIG_BOOL=n\n",
67 { .name = "bool (tristate)", .fails = 1, .cfg = CFG"CONFIG_BOOL=m" },
[all …]
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| /linux-6.12.1/drivers/net/wireless/microchip/wilc1000/ |
| D | wlan_cfg.c | 142 struct wilc_cfg *cfg = &wl->cfg; in wilc_wlan_parse_response_frame() local
150 while (cfg->b[i].id != WID_NIL && cfg->b[i].id != wid) in wilc_wlan_parse_response_frame()
153 if (cfg->b[i].id == wid) in wilc_wlan_parse_response_frame()
154 cfg->b[i].val = info[4]; in wilc_wlan_parse_response_frame()
160 while (cfg->hw[i].id != WID_NIL && cfg->hw[i].id != wid) in wilc_wlan_parse_response_frame()
163 if (cfg->hw[i].id == wid) in wilc_wlan_parse_response_frame()
164 cfg->hw[i].val = get_unaligned_le16(&info[4]); in wilc_wlan_parse_response_frame()
170 while (cfg->w[i].id != WID_NIL && cfg->w[i].id != wid) in wilc_wlan_parse_response_frame()
173 if (cfg->w[i].id == wid) in wilc_wlan_parse_response_frame()
174 cfg->w[i].val = get_unaligned_le32(&info[4]); in wilc_wlan_parse_response_frame()
[all …]
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| /linux-6.12.1/drivers/staging/media/atomisp/pci/runtime/isys/src/ |
| D | virtual_isys.c | 36 isp2401_input_system_cfg_t *cfg,
44 isp2401_input_system_cfg_t *cfg,
104 pixelgen_prbs_cfg_t *cfg);
108 csi_rx_frontend_cfg_t *cfg);
114 csi_rx_backend_cfg_t *cfg);
119 stream2mmio_cfg_t *cfg);
125 ibuf_ctrl_cfg_t *cfg);
130 isys2401_dma_cfg_t *cfg);
136 isys2401_dma_port_cfg_t *cfg);
273 isp2401_input_system_cfg_t *cfg, in create_input_system_channel() argument
[all …]
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| /linux-6.12.1/drivers/net/ethernet/cavium/thunder/ |
| D | thunder_xcv.c | 67 u64 cfg; in xcv_init_hw() local
70 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
71 cfg &= ~DLL_RESET; in xcv_init_hw()
72 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
75 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
76 cfg &= ~CLK_RESET; in xcv_init_hw()
77 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
84 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
85 cfg &= ~0xFF03; in xcv_init_hw()
86 cfg |= CLKRX_BYP; in xcv_init_hw()
[all …]
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| /linux-6.12.1/drivers/leds/ |
| D | leds-lp55xx-common.c | 92 const struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_wait_opmode_done() local
101 if (cfg->engine_busy.val) { in lp55xx_wait_opmode_done()
102 read_poll_timeout(lp55xx_read, ret, !(val & cfg->engine_busy.mask), in lp55xx_wait_opmode_done()
104 chip, cfg->engine_busy.addr, &val); in lp55xx_wait_opmode_done()
112 const struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_stop_all_engine() local
114 lp55xx_write(chip, cfg->reg_op_mode.addr, LP55xx_MODE_DISABLE_ALL_ENG); in lp55xx_stop_all_engine()
122 const struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_load_engine() local
125 mask = LP55xx_MODE_ENGn_MASK(idx, cfg->reg_op_mode.shift); in lp55xx_load_engine()
126 val = LP55xx_MODE_LOAD_ENG << LP55xx_MODE_ENGn_SHIFT(idx, cfg->reg_op_mode.shift); in lp55xx_load_engine()
128 lp55xx_update_bits(chip, cfg->reg_op_mode.addr, mask, val); in lp55xx_load_engine()
[all …]
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