Home
last modified time | relevance | path

Searched refs:cdclk_state (Results 1 – 9 of 9) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_cdclk.c2845 struct intel_cdclk_state *cdclk_state = in intel_compute_min_cdclk() local
2860 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) in intel_compute_min_cdclk()
2863 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_compute_min_cdclk()
2865 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2874 if (cdclk_state->bw_min_cdclk != min_cdclk) { in intel_compute_min_cdclk()
2877 cdclk_state->bw_min_cdclk = min_cdclk; in intel_compute_min_cdclk()
2879 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2885 min_cdclk = max(cdclk_state->force_min_cdclk, in intel_compute_min_cdclk()
2886 cdclk_state->bw_min_cdclk); in intel_compute_min_cdclk()
2888 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); in intel_compute_min_cdclk()
[all …]
Dhsw_ips.c242 const struct intel_cdclk_state *cdclk_state; in hsw_ips_compute_config() local
244 cdclk_state = intel_atomic_get_cdclk_state(state); in hsw_ips_compute_config()
245 if (IS_ERR(cdclk_state)) in hsw_ips_compute_config()
246 return PTR_ERR(cdclk_state); in hsw_ips_compute_config()
249 if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) in hsw_ips_compute_config()
Dintel_modeset_setup.c157 struct intel_cdclk_state *cdclk_state = in intel_crtc_disable_noatomic_complete() local
178 cdclk_state->min_cdclk[pipe] = 0; in intel_crtc_disable_noatomic_complete()
179 cdclk_state->min_voltage_level[pipe] = 0; in intel_crtc_disable_noatomic_complete()
180 cdclk_state->active_pipes &= ~BIT(pipe); in intel_crtc_disable_noatomic_complete()
698 struct intel_cdclk_state *cdclk_state = in intel_modeset_readout_hw_state() local
735 cdclk_state->active_pipes = active_pipes; in intel_modeset_readout_hw_state()
893 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_modeset_readout_hw_state()
894 cdclk_state->min_voltage_level[crtc->pipe] = in intel_modeset_readout_hw_state()
Dintel_display_driver.c85 struct intel_cdclk_state *cdclk_state; in intel_display_driver_init_hw() local
90 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_display_driver_init_hw()
94 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_display_driver_init_hw()
Dintel_atomic_plane.c273 const struct intel_cdclk_state *cdclk_state; in intel_plane_calc_min_cdclk() local
298 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_plane_calc_min_cdclk()
299 if (IS_ERR(cdclk_state)) in intel_plane_calc_min_cdclk()
300 return PTR_ERR(cdclk_state); in intel_plane_calc_min_cdclk()
311 cdclk_state->min_cdclk[crtc->pipe]) in intel_plane_calc_min_cdclk()
319 cdclk_state->min_cdclk[crtc->pipe]); in intel_plane_calc_min_cdclk()
Dintel_bw.c1270 const struct intel_cdclk_state *cdclk_state; in intel_bw_calc_min_cdclk() local
1315 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_bw_calc_min_cdclk()
1316 if (IS_ERR(cdclk_state)) in intel_bw_calc_min_cdclk()
1317 return PTR_ERR(cdclk_state); in intel_bw_calc_min_cdclk()
1327 if (new_min_cdclk <= cdclk_state->bw_min_cdclk) in intel_bw_calc_min_cdclk()
1332 new_min_cdclk, cdclk_state->bw_min_cdclk); in intel_bw_calc_min_cdclk()
Dintel_audio.c927 struct intel_cdclk_state *cdclk_state; in glk_force_audio_cdclk_commit() local
935 cdclk_state = intel_atomic_get_cdclk_state(state); in glk_force_audio_cdclk_commit()
936 if (IS_ERR(cdclk_state)) in glk_force_audio_cdclk_commit()
937 return PTR_ERR(cdclk_state); in glk_force_audio_cdclk_commit()
939 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; in glk_force_audio_cdclk_commit()
Dintel_fbc.c1413 const struct intel_cdclk_state *cdclk_state; in intel_fbc_check_plane() local
1415 cdclk_state = intel_atomic_get_cdclk_state(state); in intel_fbc_check_plane()
1416 if (IS_ERR(cdclk_state)) in intel_fbc_check_plane()
1417 return PTR_ERR(cdclk_state); in intel_fbc_check_plane()
1419 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) { in intel_fbc_check_plane()
Dintel_display.c4202 const struct intel_cdclk_state *cdclk_state) in hsw_ips_linetime_wm() argument
4212 cdclk_state->logical.cdclk); in hsw_ips_linetime_wm()
4245 const struct intel_cdclk_state *cdclk_state; in hsw_compute_linetime_wm() local
4255 cdclk_state = intel_atomic_get_cdclk_state(state); in hsw_compute_linetime_wm()
4256 if (IS_ERR(cdclk_state)) in hsw_compute_linetime_wm()
4257 return PTR_ERR(cdclk_state); in hsw_compute_linetime_wm()
4260 cdclk_state); in hsw_compute_linetime_wm()