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Searched refs:ccs_mask (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_irq.c132 u32 ccs_mask, bcs_mask; in xe_irq_enable_hwe() local
150 ccs_mask = xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_COMPUTE); in xe_irq_enable_hwe()
159 if (ccs_mask) in xe_irq_enable_hwe()
173 if (ccs_mask & (BIT(0)|BIT(1))) in xe_irq_enable_hwe()
175 if (ccs_mask & (BIT(2)|BIT(3))) in xe_irq_enable_hwe()
479 u32 ccs_mask = xe_hw_engine_mask_per_class(tile->primary_gt, in gt_irq_reset() local
487 if (ccs_mask) in gt_irq_reset()
504 if (ccs_mask & (BIT(0)|BIT(1))) in gt_irq_reset()
506 if (ccs_mask & (BIT(2)|BIT(3))) in gt_irq_reset()
Dxe_hw_engine.c323 u32 ccs_mask = in xe_hw_engine_enable_ring() local
326 if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask) in xe_hw_engine_enable_ring()
705 u32 ccs_mask; in read_compute_fuses_from_reg() local
707 ccs_mask = xe_mmio_read32(gt, XEHP_FUSE4); in read_compute_fuses_from_reg()
708 ccs_mask = REG_FIELD_GET(CCS_EN_MASK, ccs_mask); in read_compute_fuses_from_reg()
714 if ((ccs_mask & BIT(j)) == 0) { in read_compute_fuses_from_reg()
/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dintel_engine_cs.c822 unsigned long ccs_mask; in engine_mask_apply_compute_fuses() local
831 ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, in engine_mask_apply_compute_fuses()
837 for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) { in engine_mask_apply_compute_fuses()