| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 334 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size); in dcn30_fpu_populate_dml_writeback_from_context()
371 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || in dcn30_fpu_update_soc_for_wm_a()
372 context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0) in dcn30_fpu_update_soc_for_wm_a()
373 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_update_soc_for_wm_a()
374 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_update_soc_for_wm_a()
375 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_in… in dcn30_fpu_update_soc_for_wm_a()
385 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb; in dcn30_fpu_calculate_wm_and_dlg()
387 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb]; in dcn30_fpu_calculate_wm_and_dlg()
388 …bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clo… in dcn30_fpu_calculate_wm_and_dlg()
394 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn30_fpu_calculate_wm_and_dlg()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.c | 459 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
460 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
471 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[context->bw_ctx.dml.vba.VoltageLevel][context->… in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latenc… in dcn315_update_soc_for_wm_a()
474 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
475 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn315_update_soc_for_wm_a()
477 context->bw_ctx.dml.soc.sr_exit_time_us = in dcn315_update_soc_for_wm_a()
489 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
494 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn31_calculate_wm_and_dlg_fp()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 282 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
284 …temp_clock_change_support = vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
290 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
291 context->bw_ctx.dml.soc.dram_clock_change_latency_us = in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
298 …vba->DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] = temp_clock_change_suppor… in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
300 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
350 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
352 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
354 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
356 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 1040 …wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) *… in dcn20_fpu_set_wb_arb_params()
1041 …wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipe… in dcn20_fpu_set_wb_arb_params()
1086 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in decide_zstate_support()
1096 if (is_pwrseq0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0) in decide_zstate_support()
1154 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
1155 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
1156 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
1157 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
1159 if (dc->debug.min_dram_clk_khz > context->bw_ctx.bw.dcn.clk.dramclk_khz) in dcn20_calculate_dlg_params()
1160 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz; in dcn20_calculate_dlg_params()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/ |
| D | dml2_utils.c | 184 context->bw_ctx.bw.dcn.clk.dispclk_khz = out_clks->dispclk_khz; in dml2_copy_clocks_to_dc_state()
185 context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz; in dml2_copy_clocks_to_dc_state()
186 context->bw_ctx.bw.dcn.clk.dramclk_khz = out_clks->uclk_mts / 16; in dml2_copy_clocks_to_dc_state()
187 context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz; in dml2_copy_clocks_to_dc_state()
188 context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz; in dml2_copy_clocks_to_dc_state()
189 context->bw_ctx.bw.dcn.clk.socclk_khz = out_clks->socclk_khz; in dml2_copy_clocks_to_dc_state()
190 context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = out_clks->ref_dtbclk_khz; in dml2_copy_clocks_to_dc_state()
191 context->bw_ctx.bw.dcn.clk.p_state_change_support = out_clks->p_state_supported; in dml2_copy_clocks_to_dc_state()
285 …context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (unsigned int)in_ctx->v20.dml_core_ctx.mp.DCFCL… in dml2_calculate_rq_and_dlg_params()
286 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml2_calculate_rq_and_dlg_params()
[all …]
|
| D | dml2_wrapper.c | 446 display_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in optimize_pstate_with_svp_and_drr()
447 display_state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid = false; in optimize_pstate_with_svp_and_drr()
459 display_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = true; in optimize_pstate_with_svp_and_drr()
499 display_state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid = true; in optimize_pstate_with_svp_and_drr()
500 display_state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index = drr_display_index; in optimize_pstate_with_svp_and_drr()
525 display_state->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in optimize_pstate_with_svp_and_drr()
526 display_state->bw_ctx.bw.dcn.legacy_svp_drr_stream_index_valid = false; in optimize_pstate_with_svp_and_drr()
538 struct dml2_context *dml2 = context->bw_ctx.dml2; in call_dml_mode_support_and_programming()
567 struct dml2_context *dml2 = context->bw_ctx.dml2; in dml2_validate_and_build_resource()
585 context->bw_ctx.bw.dcn.clk.dtbclk_en = false; in dml2_validate_and_build_resource()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| D | dml21_wrapper.c | 129 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml21_calculate_rq_and_dlg_params()
132 …memcpy(&context->bw_ctx.bw.dcn.arb_regs, &in_ctx->v21.mode_programming.programming->global_regs.ar… in dml21_calculate_rq_and_dlg_params()
135 …context->bw_ctx.bw.dcn.compbuf_size_kb = (int)in_ctx->v21.mode_programming.programming->global_reg… in dml21_calculate_rq_and_dlg_params()
137 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
138 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
139 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
169 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dml21_calculate_rq_and_dlg_params()
170 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dml21_calculate_rq_and_dlg_params()
172 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in dml21_calculate_rq_and_dlg_params()
175 …context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispc… in dml21_calculate_rq_and_dlg_params()
[all …]
|
| D | dml21_utils.c | 264 context->bw_ctx.bw.dcn.mall_ss_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
268 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
330 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz) in dml21_program_dc_pipe()
331 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz; in dml21_program_dc_pipe()
334 …memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[pipe_ctx->pipe_idx], &pln_prog->mcache_allocatio… in dml21_program_dc_pipe()
485 …memset(&context->bw_ctx.bw.dcn.fams2_stream_params, 0, sizeof(struct dmub_fams2_stream_static_stat… in dml21_build_fams2_programming()
486 …memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config)… in dml21_build_fams2_programming()
494 …struct dmub_fams2_stream_static_state *static_state = &context->bw_ctx.bw.dcn.fams2_stream_params[… in dml21_build_fams2_programming()
571 memcpy(&context->bw_ctx.bw.dcn.fams2_global_config, in dml21_build_fams2_programming()
575 context->bw_ctx.bw.dcn.fams2_global_config.num_streams = num_fams2_streams; in dml21_build_fams2_programming()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_state.c | 189 memcpy(&state->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); in init_state()
214 if (!dml2_create(dc, dml2_opt, &state->bw_ctx.dml2)) { in dc_state_create()
220 if (!dml2_create(dc, dml2_opt, &state->bw_ctx.dml2_dc_power_source)) { in dc_state_create()
236 struct dml2_context *dst_dml2 = dst_state->bw_ctx.dml2; in dc_state_copy()
237 struct dml2_context *dst_dml2_dc_power_source = dst_state->bw_ctx.dml2_dc_power_source; in dc_state_copy()
243 dst_state->bw_ctx.dml2 = dst_dml2; in dc_state_copy()
244 if (src_state->bw_ctx.dml2) in dc_state_copy()
245 dml2_copy(dst_state->bw_ctx.dml2, src_state->bw_ctx.dml2); in dc_state_copy()
247 dst_state->bw_ctx.dml2_dc_power_source = dst_dml2_dc_power_source; in dc_state_copy()
248 if (src_state->bw_ctx.dml2_dc_power_source) in dc_state_copy()
[all …]
|
| D | dc_debug.c | 353 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
354 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
355 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
356 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
357 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
358 context->bw_ctx.bw.dcn.clk.socclk_khz); in context_clock_trace()
361 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
362 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
363 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
364 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| D | dce112_resource.c | 903 &context->bw_ctx.bw.dce)) in dce112_validate_bandwidth()
911 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce112_validate_bandwidth()
912 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce112_validate_bandwidth()
926 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, in dce112_validate_bandwidth()
927 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, in dce112_validate_bandwidth()
928 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce112_validate_bandwidth()
929 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce112_validate_bandwidth()
930 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, in dce112_validate_bandwidth()
931 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, in dce112_validate_bandwidth()
932 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, in dce112_validate_bandwidth()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| D | dce110_clk_mgr.c | 183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
211 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
224 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
255 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| D | dcn_calcs.c | 566 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
568 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
570 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
572 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
573 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
580 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
582 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
584 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
586 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
587 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| D | dce110_resource.c | 980 &context->bw_ctx.bw.dce)) in dce110_validate_bandwidth()
990 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce110_validate_bandwidth()
991 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce110_validate_bandwidth()
1005 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1006 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1007 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1008 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1009 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1010 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1011 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, in dce110_validate_bandwidth()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| D | dcn301_fpu.c | 434 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn301_fpu_calculate_wm_and_dlg()
435 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
439 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, in dcn301_fpu_calculate_wm_and_dlg()
440 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
444 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, in dcn301_fpu_calculate_wm_and_dlg()
445 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
450 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, in dcn301_fpu_calculate_wm_and_dlg()
451 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
457 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn301_fpu_calculate_wm_and_dlg()
458 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn301_fpu_calculate_wm_and_dlg()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clk_mgr.c | 227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
619 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
623 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
625 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
627 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
629 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
634 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
647 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| D | dcn35_fpu.c | 528 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/ in dcn35_populate_dml_pipes_from_context_fpu()
542 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn35_populate_dml_pipes_from_context_fpu()
548 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn35_populate_dml_pipes_from_context_fpu()
551 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn35_populate_dml_pipes_from_context_fpu()
566 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn35_populate_dml_pipes_from_context_fpu()
597 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn35_decide_zstate_support()
600 bool allow_z10 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z10_residency; in dcn35_decide_zstate_support()
613 (int)context->bw_ctx.dml.vba.StutterPeriod); in dcn35_decide_zstate_support()
615 context->bw_ctx.bw.dcn.clk.zstate_support = support; in dcn35_decide_zstate_support()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| D | dcn351_fpu.c | 562 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 384;/*per guide*/ in dcn351_populate_dml_pipes_from_context_fpu()
576 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn351_populate_dml_pipes_from_context_fpu()
582 context->bw_ctx.dml.ip.det_buffer_size_kbytes = in dcn351_populate_dml_pipes_from_context_fpu()
585 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn351_populate_dml_pipes_from_context_fpu()
600 context->bw_ctx.dml.vba.ODMCombinePolicy = in dcn351_populate_dml_pipes_from_context_fpu()
631 bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency; in dcn351_decide_zstate_support()
637 context->bw_ctx.bw.dcn.clk.zstate_support = support; in dcn351_decide_zstate_support()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| D | dcn30_resource.c | 1381 struct display_mode_lib *dml = &context->bw_ctx.dml; in dcn30_set_mcif_arb_params()
1399 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; in dcn30_set_mcif_arb_params()
1640 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw()
1646 context->bw_ctx.dml.vba.maxMpcComb = 0; in dcn30_internal_validate_bw()
1647 context->bw_ctx.dml.vba.VoltageLevel = 0; in dcn30_internal_validate_bw()
1648 context->bw_ctx.dml.vba.DRAMClockChangeSupport[0][0] = dm_dram_clock_change_vactive; in dcn30_internal_validate_bw()
1657 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1665 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn30_internal_validate_bw()
1667 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_internal_validate_bw()
1669 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | dcn314_fpu.c | 392 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_14_DEFAULT_DET_SIZE; in dcn314_populate_dml_pipes_from_context_fpu()
402 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
407 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64; in dcn314_populate_dml_pipes_from_context_fpu()
409 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn314_populate_dml_pipes_from_context_fpu()
422 context->bw_ctx.dml.vba.ODMCombinePolicy = dm_odm_combine_policy_2to1; in dcn314_populate_dml_pipes_from_context_fpu()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks()
349 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks_fpga()
456 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
459 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
462 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
465 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; in dcn2_get_clock()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| D | dcn21_resource.c | 801 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
803 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
805 if (vlevel > context->bw_ctx.dml.soc.num_states) { in dcn21_fast_validate_bw()
813 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank = in dcn21_fast_validate_bw()
815 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_fast_validate_bw()
816 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn21_fast_validate_bw()
825 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn21_fast_validate_bw()
855 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
879 …dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe… in dcn21_fast_validate_bw()
883 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| D | dcn401_hwseq.c | 53 struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; in dcn401_initialize_min_clocks()
1273 mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes; in dcn401_calculate_cab_allocation()
1401 bool p_state_change_support = context->bw_ctx.bw.dcn.clk.p_state_change_support; in dcn401_prepare_bandwidth()
1407 context->bw_ctx.bw.dcn.clk.p_state_change_support = false; in dcn401_prepare_bandwidth()
1412 context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000) in dcn401_prepare_bandwidth()
1426 &context->bw_ctx.bw.dcn.watermarks, in dcn401_prepare_bandwidth()
1432 compbuf_size = context->bw_ctx.bw.dcn.arb_regs.compbuf_size; in dcn401_prepare_bandwidth()
1433 …dc->wm_optimized_required |= (compbuf_size != dc->current_state->bw_ctx.bw.dcn.arb_regs.compbuf_si… in dcn401_prepare_bandwidth()
1444 if (p_state_change_support != context->bw_ctx.bw.dcn.clk.p_state_change_support) { in dcn401_prepare_bandwidth()
1447 context->bw_ctx.bw.dcn.clk.p_state_change_support = p_state_change_support; in dcn401_prepare_bandwidth()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer_debug.c | 476 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_get_clock_states()
477 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_get_clock_states()
478 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_get_clock_states()
479 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_get_clock_states()
480 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_get_clock_states()
481 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_get_clock_states()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| D | dcn32_resource_helpers.c | 94 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) { in dcn32_helper_calculate_num_ways_for_subvp()
98 …return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_s… in dcn32_helper_calculate_num_ways_for_subvp()
533 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching_shut_down) in dcn32_can_support_mclk_switch_using_fw_based_vblank_stretch()
711 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn32_subvp_vblank_admissable()
778 …if (dcn32_subvp_in_use(dc, context) && context->bw_ctx.bw.dcn.clk.dcfclk_khz <= MIN_SUBVP_DCFCLK_K… in dcn32_override_min_req_dcfclk()
779 context->bw_ctx.bw.dcn.clk.dcfclk_khz = MIN_SUBVP_DCFCLK_KHZ; in dcn32_override_min_req_dcfclk()
|