Searched refs:block_sequence (Results 1 – 7 of 7) sorted by relevance
580 struct block_sequence block_sequence[], in hwss_build_fast_sequence() argument599 block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.dc = dc; in hwss_build_fast_sequence()600 …block_sequence[*num_steps].params.wait_for_dcc_meta_propagation_params.top_pipe_to_program = pipe_… in hwss_build_fast_sequence()601 block_sequence[*num_steps].func = HUBP_WAIT_FOR_DCC_META_PROP; in hwss_build_fast_sequence()605 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.dc = dc; in hwss_build_fast_sequence()606 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.lock = true; in hwss_build_fast_sequence()607 block_sequence[*num_steps].params.subvp_pipe_control_lock_fast_params.subvp_immediate_flip = in hwss_build_fast_sequence()609 block_sequence[*num_steps].func = DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST; in hwss_build_fast_sequence()613 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.dc = dc; in hwss_build_fast_sequence()614 block_sequence[*num_steps].params.fams2_global_control_lock_fast_params.lock = true; in hwss_build_fast_sequence()[all …]
342 memset(state->block_sequence, 0, sizeof(state->block_sequence)); in dc_state_destruct()
3711 context->block_sequence, in commit_planes_for_stream_fast()3717 context->block_sequence, in commit_planes_for_stream_fast()
828 params = &clk_mgr401->block_sequence[i].params; in dcn401_execute_block_sequence()830 switch (clk_mgr401->block_sequence[i].func) { in dcn401_execute_block_sequence()942 struct dcn401_clk_mgr_block_sequence *block_sequence = clk_mgr401->block_sequence; in dcn401_build_update_bandwidth_clocks_sequence() local971 block_sequence[num_steps].params.update_num_displays_params.num_displays = display_count; in dcn401_build_update_bandwidth_clocks_sequence()972 block_sequence[num_steps].func = CLK_MGR401_UPDATE_NUM_DISPLAYS; in dcn401_build_update_bandwidth_clocks_sequence()989 block_sequence[num_steps].params.update_pstate_support_params.support = true; in dcn401_build_update_bandwidth_clocks_sequence()990 block_sequence[num_steps].func = CLK_MGR401_UPDATE_FCLK_PSTATE_SUPPORT; in dcn401_build_update_bandwidth_clocks_sequence()1011 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK; in dcn401_build_update_bandwidth_clocks_sequence()1012 …block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->cl… in dcn401_build_update_bandwidth_clocks_sequence()1013 block_sequence[num_steps].params.update_hardmin_params.response = NULL; in dcn401_build_update_bandwidth_clocks_sequence()[all …]
103 struct dcn401_clk_mgr_block_sequence block_sequence[DCN401_CLK_MGR_MAX_SEQUENCE_SIZE]; member
200 struct block_sequence { struct513 struct block_sequence block_sequence[],519 struct block_sequence block_sequence[],
623 struct block_sequence block_sequence[50]; member