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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/spl/
Ddc_spl.c1622 dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format in spl_set_isharp_data()
1626 …dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format in spl_set_isharp_data()
1630 …dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format in spl_set_isharp_data()
1634 dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format in spl_set_isharp_data()
1638 dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format in spl_set_isharp_data()
1642 dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format in spl_set_isharp_data()
1646 dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format in spl_set_isharp_data()
1650 …dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format in spl_set_isharp_data()
1654 …dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format in spl_set_isharp_data()
1658 dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format in spl_set_isharp_data()
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Ddc_spl_types.h236 uint32_t base_seg[6]; member
/linux-6.12.1/lib/
Dassoc_array.c482 unsigned long dissimilarity, base_seg, blank; in assoc_array_insert_into_terminal_node() local
558 base_seg = ops->get_object_key_chunk( in assoc_array_insert_into_terminal_node()
560 base_seg >>= level & ASSOC_ARRAY_KEY_CHUNK_MASK; in assoc_array_insert_into_terminal_node()
561 edit->segment_cache[i] = base_seg & ASSOC_ARRAY_FAN_MASK; in assoc_array_insert_into_terminal_node()
571 base_seg = edit->segment_cache[0]; in assoc_array_insert_into_terminal_node()
573 dissimilarity |= edit->segment_cache[i] ^ base_seg; in assoc_array_insert_into_terminal_node()
581 if ((edit->segment_cache[ASSOC_ARRAY_FAN_OUT] ^ base_seg) == 0) in assoc_array_insert_into_terminal_node()
777 base_seg = ops->get_object_key_chunk(assoc_array_ptr_to_leaf(ptr), in assoc_array_insert_into_terminal_node()
779 base_seg >>= level & ASSOC_ARRAY_KEY_CHUNK_MASK; in assoc_array_insert_into_terminal_node()
780 edit->segment_cache[i] = base_seg & ASSOC_ARRAY_FAN_MASK; in assoc_array_insert_into_terminal_node()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
Ddcn401_dpp_dscl.c998 ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0], in dpp401_dscl_program_isharp()
1002 ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1], in dpp401_dscl_program_isharp()
1006 ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2], in dpp401_dscl_program_isharp()
1010 ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3], in dpp401_dscl_program_isharp()
1014 ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4], in dpp401_dscl_program_isharp()
1018 ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]); in dpp401_dscl_program_isharp()