Searched refs:base_dma (Results 1 – 8 of 8) sorted by relevance
/linux-6.12.1/drivers/dma/sh/ |
D | rz-dmac.c | 86 dma_addr_t base_dma; member 223 nxla = channel->lmdesc.base_dma; in rz_lmdesc_setup() 232 lmdesc->nxla = channel->lmdesc.base_dma; in rz_lmdesc_setup() 268 nxla = channel->lmdesc.base_dma + in rz_dmac_enable_hw() 807 &channel->lmdesc.base_dma, GFP_KERNEL); in rz_dmac_chan_probe() 963 channel->lmdesc.base_dma); in rz_dmac_probe() 988 channel->lmdesc.base_dma); in rz_dmac_remove()
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/linux-6.12.1/drivers/crypto/inside-secure/ |
D | safexcel_ring.c | 25 &cdr->base_dma, GFP_KERNEL); in safexcel_init_ring_descriptors() 62 &rdr->base_dma, GFP_KERNEL); in safexcel_init_ring_descriptors()
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D | safexcel.c | 512 writel(lower_32_bits(priv->ring[i].cdr.base_dma), in safexcel_hw_setup_cdesc_rings() 514 writel(upper_32_bits(priv->ring[i].cdr.base_dma), in safexcel_hw_setup_cdesc_rings() 560 writel(lower_32_bits(priv->ring[i].rdr.base_dma), in safexcel_hw_setup_rdesc_rings() 562 writel(upper_32_bits(priv->ring[i].rdr.base_dma), in safexcel_hw_setup_rdesc_rings()
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D | safexcel.h | 656 dma_addr_t base_dma; member
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/linux-6.12.1/drivers/mtd/nand/raw/ |
D | qcom_nandc.c | 430 dma_addr_t base_dma; member 1064 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc() 1072 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc() 3411 nandc->base_dma = dma_map_resource(dev, res->start, in qcom_nandc_probe() 3414 if (dma_mapping_error(dev, nandc->base_dma)) in qcom_nandc_probe() 3446 dma_unmap_resource(dev, nandc->base_dma, resource_size(res), in qcom_nandc_probe() 3471 dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res), in qcom_nandc_remove()
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/linux-6.12.1/drivers/iommu/arm/arm-smmu-v3/ |
D | tegra241-cmdqv.c | 499 dmam_free_coherent(vcmdq->cmdqv->smmu.dev, qsz, q->base, q->base_dma); in tegra241_vcmdq_free_smmu_cmdq() 522 q->q_base = q->base_dma & VCMDQ_ADDR; in tegra241_vcmdq_alloc_smmu_cmdq()
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D | arm-smmu-v3.h | 586 dma_addr_t base_dma; member
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D | arm-smmu-v3.c | 382 ent.sync.msiaddr = q->base_dma + Q_IDX(&q->llq, prod) * in arm_smmu_cmdq_build_sync_cmd() 3537 q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma, in arm_smmu_init_one_queue() 3552 if (!WARN_ON(q->base_dma & (qsz - 1))) { in arm_smmu_init_one_queue() 3562 q->q_base |= q->base_dma & Q_BASE_ADDR_MASK; in arm_smmu_init_one_queue()
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