| /linux-6.12.1/drivers/gpio/ |
| D | gpio-omap.c | 78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) argument
109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, in omap_set_gpio_dataout_reg() argument
121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
125 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
126 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
128 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
129 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
[all …]
|
| D | gpio-rockchip.c | 76 static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, in rockchip_gpio_writel() argument
79 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel()
81 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_writel()
87 static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, in rockchip_gpio_readl() argument
90 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_readl()
93 if (bank->gpio_type == GPIO_TYPE_V2) in rockchip_gpio_readl()
101 static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_writel_bit() argument
105 void __iomem *reg = bank->reg_base + offset; in rockchip_gpio_writel_bit()
108 if (bank->gpio_type == GPIO_TYPE_V2) { in rockchip_gpio_writel_bit()
123 static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, in rockchip_gpio_readl_bit() argument
[all …]
|
| D | gpio-brcmstb.c | 26 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
27 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
28 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
29 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
30 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
31 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
32 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
33 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
34 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
65 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); in brcmstb_gpio_gc_to_priv() local
[all …]
|
| /linux-6.12.1/drivers/pinctrl/samsung/ |
| D | pinctrl-exynos.c | 55 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in exynos_irq_mask() local
60 if (bank->eint_mask_offset) in exynos_irq_mask()
61 reg_mask = bank->pctl_offset + bank->eint_mask_offset; in exynos_irq_mask()
63 reg_mask = our_chip->eint_mask + bank->eint_offset; in exynos_irq_mask()
65 if (clk_enable(bank->drvdata->pclk)) { in exynos_irq_mask()
66 dev_err(bank->gpio_chip.parent, in exynos_irq_mask()
71 raw_spin_lock_irqsave(&bank->slock, flags); in exynos_irq_mask()
73 mask = readl(bank->eint_base + reg_mask); in exynos_irq_mask()
75 writel(mask, bank->eint_base + reg_mask); in exynos_irq_mask()
77 raw_spin_unlock_irqrestore(&bank->slock, flags); in exynos_irq_mask()
[all …]
|
| D | pinctrl-samsung.c | 356 struct samsung_pin_bank **bank) in pin_to_reg_bank() argument
368 if (bank) in pin_to_reg_bank()
369 *bank = b; in pin_to_reg_bank()
378 struct samsung_pin_bank *bank; in samsung_pinmux_setup() local
390 pin_to_reg_bank(drvdata, grp->pins[0], ®, &pin_offset, &bank); in samsung_pinmux_setup()
391 type = bank->type; in samsung_pinmux_setup()
406 raw_spin_lock_irqsave(&bank->slock, flags); in samsung_pinmux_setup()
413 raw_spin_unlock_irqrestore(&bank->slock, flags); in samsung_pinmux_setup()
442 struct samsung_pin_bank *bank; in samsung_pinconf_rw() local
451 pin_to_reg_bank(drvdata, pin, ®_base, &pin_offset, &bank); in samsung_pinconf_rw()
[all …]
|
| D | pinctrl-s3c64xx.c | 217 struct samsung_pin_bank *bank; member
281 struct samsung_pin_bank *bank, int pin) in s3c64xx_irq_set_function() argument
283 const struct samsung_pin_bank_type *bank_type = bank->type; in s3c64xx_irq_set_function()
291 reg = d->virt_base + bank->pctl_offset; in s3c64xx_irq_set_function()
302 raw_spin_lock_irqsave(&bank->slock, flags); in s3c64xx_irq_set_function()
306 val |= bank->eint_func << shift; in s3c64xx_irq_set_function()
309 raw_spin_unlock_irqrestore(&bank->slock, flags); in s3c64xx_irq_set_function()
318 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); in s3c64xx_gpio_irq_set_mask() local
319 struct samsung_pinctrl_drv_data *d = bank->drvdata; in s3c64xx_gpio_irq_set_mask()
320 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_set_mask()
[all …]
|
| /linux-6.12.1/drivers/crypto/intel/qat/qat_common/ |
| D | adf_gen4_hw_csr_data.h | 37 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
39 ADF_RING_BUNDLE_SIZE * (bank) + \
41 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
43 ADF_RING_BUNDLE_SIZE * (bank) + \
45 #define READ_CSR_STAT(csr_base_addr, bank) \ argument
47 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_STAT)
48 #define READ_CSR_UO_STAT(csr_base_addr, bank) \ argument
50 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_UO_STAT)
51 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
53 ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
[all …]
|
| D | adf_gen4_hw_csr_data.c | 11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_stat() argument
35 return READ_CSR_STAT(csr_base_addr, bank); in read_csr_stat()
[all …]
|
| D | adf_transport.c | 40 static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_reserve_ring() argument
42 spin_lock(&bank->lock); in adf_reserve_ring()
43 if (bank->ring_mask & (1 << ring)) { in adf_reserve_ring()
44 spin_unlock(&bank->lock); in adf_reserve_ring()
47 bank->ring_mask |= (1 << ring); in adf_reserve_ring()
48 spin_unlock(&bank->lock); in adf_reserve_ring()
52 static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) in adf_unreserve_ring() argument
54 spin_lock(&bank->lock); in adf_unreserve_ring()
55 bank->ring_mask &= ~(1 << ring); in adf_unreserve_ring()
56 spin_unlock(&bank->lock); in adf_unreserve_ring()
[all …]
|
| D | adf_gen2_hw_csr_data.h | 30 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \ argument
31 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
33 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \ argument
34 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
36 #define READ_CSR_E_STAT(csr_base_addr, bank) \ argument
37 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
39 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \ argument
40 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
42 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \ argument
47 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
[all …]
|
| D | adf_gen2_hw_csr_data.c | 11 static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_head() argument
13 return READ_CSR_RING_HEAD(csr_base_addr, bank, ring); in read_csr_ring_head()
16 static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_head() argument
19 WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value); in write_csr_ring_head()
22 static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring) in read_csr_ring_tail() argument
24 return READ_CSR_RING_TAIL(csr_base_addr, bank, ring); in read_csr_ring_tail()
27 static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring, in write_csr_ring_tail() argument
30 WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value); in write_csr_ring_tail()
33 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank) in read_csr_e_stat() argument
35 return READ_CSR_E_STAT(csr_base_addr, bank); in read_csr_e_stat()
[all …]
|
| D | adf_transport_debug.c | 44 struct adf_etr_bank_data *bank = ring->bank; in adf_ring_show() local
45 struct adf_hw_csr_ops *csr_ops = GET_CSR_OPS(bank->accel_dev); in adf_ring_show()
46 void __iomem *csr = ring->bank->csr_addr; in adf_ring_show()
51 head = csr_ops->read_csr_ring_head(csr, bank->bank_number, in adf_ring_show()
53 tail = csr_ops->read_csr_ring_tail(csr, bank->bank_number, in adf_ring_show()
55 empty = csr_ops->read_csr_e_stat(csr, bank->bank_number); in adf_ring_show()
61 ring->ring_number, ring->bank->bank_number); in adf_ring_show()
104 ring->bank->bank_debug_dir, in adf_ring_debugfs_add()
121 struct adf_etr_bank_data *bank = sfile->private; in adf_bank_start() local
122 u8 num_rings_per_bank = GET_NUM_RINGS_PER_BANK(bank->accel_dev); in adf_bank_start()
[all …]
|
| /linux-6.12.1/drivers/pinctrl/renesas/ |
| D | sh_pfc.h | 442 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
443 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
444 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
446 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument
447 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
448 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
449 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) argument
451 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
452 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
453 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
[all …]
|
| /linux-6.12.1/arch/x86/kernel/cpu/mce/ |
| D | amd.c | 134 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank) in smca_get_bank_type() argument
138 if (bank >= MAX_NR_BANKS) in smca_get_bank_type()
141 b = &per_cpu(smca_banks, cpu)[bank]; in smca_get_bank_type()
244 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) in smca_set_misc_banks_map() argument
252 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) in smca_set_misc_banks_map()
258 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high)) in smca_set_misc_banks_map()
262 per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank); in smca_set_misc_banks_map()
266 static void smca_configure(unsigned int bank, unsigned int cpu) in smca_configure() argument
272 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); in smca_configure()
301 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); in smca_configure()
[all …]
|
| D | threshold.c | 35 void mce_inherit_storm(unsigned int bank) in mce_inherit_storm() argument
46 storm->banks[bank].history = ~0ull; in mce_inherit_storm()
47 storm->banks[bank].timestamp = jiffies; in mce_inherit_storm()
60 static void mce_handle_storm(unsigned int bank, bool on) in mce_handle_storm() argument
64 mce_intel_handle_storm(bank, on); in mce_handle_storm()
69 void cmci_storm_begin(unsigned int bank) in cmci_storm_begin() argument
73 __set_bit(bank, this_cpu_ptr(mce_poll_banks)); in cmci_storm_begin()
74 storm->banks[bank].in_storm_mode = true; in cmci_storm_begin()
84 void cmci_storm_end(unsigned int bank) in cmci_storm_end() argument
88 __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); in cmci_storm_end()
[all …]
|
| D | intel.c | 137 static void cmci_set_threshold(int bank, int thresh) in cmci_set_threshold() argument
143 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); in cmci_set_threshold()
145 wrmsrl(MSR_IA32_MCx_CTL2(bank), val | thresh); in cmci_set_threshold()
149 void mce_intel_handle_storm(int bank, bool on) in mce_intel_handle_storm() argument
152 cmci_set_threshold(bank, CMCI_STORM_THRESHOLD); in mce_intel_handle_storm()
154 cmci_set_threshold(bank, cmci_threshold[bank]); in mce_intel_handle_storm()
175 static bool cmci_skip_bank(int bank, u64 *val) in cmci_skip_bank() argument
179 if (test_bit(bank, owned)) in cmci_skip_bank()
183 if (test_bit(bank, mce_banks_ce_disabled)) in cmci_skip_bank()
186 rdmsrl(MSR_IA32_MCx_CTL2(bank), *val); in cmci_skip_bank()
[all …]
|
| D | internal.h | 44 void mce_intel_handle_storm(int bank, bool on);
45 void cmci_disable_bank(int bank);
52 static inline void mce_intel_handle_storm(int bank, bool on) { } in mce_intel_handle_storm() argument
53 static inline void cmci_disable_bank(int bank) { } in cmci_disable_bank() argument
64 void cmci_storm_begin(unsigned int bank);
65 void cmci_storm_end(unsigned int bank);
67 void mce_inherit_storm(unsigned int bank);
71 static inline void cmci_storm_begin(unsigned int bank) {} in cmci_storm_begin() argument
72 static inline void cmci_storm_end(unsigned int bank) {} in cmci_storm_end() argument
74 static inline void mce_inherit_storm(unsigned int bank) {} in mce_inherit_storm() argument
[all …]
|
| /linux-6.12.1/drivers/pinctrl/stm32/ |
| D | pinctrl-stm32.c | 157 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank, in stm32_gpio_backup_value() argument
160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
164 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_mode() argument
167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
169 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
170 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
173 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset, in stm32_gpio_backup_driving() argument
176 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
177 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
[all …]
|
| /linux-6.12.1/tools/testing/selftests/gpio/ |
| D | gpio-sim.sh | 181 create_bank chip bank
183 test -n `cat $CONFIGFS_DIR/chip/bank/chip_name` || fail "chip_name doesn't work"
188 create_bank chip bank
195 create_bank chip bank
204 create_bank chip bank
211 create_bank chip bank
212 set_num_lines chip bank 16
219 create_bank chip bank
220 set_label chip bank foobar
227 create_bank chip bank
[all …]
|
| /linux-6.12.1/drivers/net/phy/mscc/ |
| D | mscc_macsec.c | 23 enum macsec_bank bank, u32 reg) in vsc8584_macsec_phy_read() argument
34 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_read()
36 if (bank >> 2 == 0x1) in vsc8584_macsec_phy_read()
38 bank &= 0x3; in vsc8584_macsec_phy_read()
40 bank = 0; in vsc8584_macsec_phy_read()
45 MSCC_PHY_MACSEC_19_TARGET(bank)); in vsc8584_macsec_phy_read()
62 enum macsec_bank bank, u32 reg, u32 val) in vsc8584_macsec_phy_write() argument
72 MSCC_PHY_MACSEC_20_TARGET(bank >> 2)); in vsc8584_macsec_phy_write()
74 if ((bank >> 2 == 0x1) || (bank >> 2 == 0x3)) in vsc8584_macsec_phy_write()
75 bank &= 0x3; in vsc8584_macsec_phy_write()
[all …]
|
| /linux-6.12.1/drivers/bus/ |
| D | uniphier-system-bus.c | 35 struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; member
39 int bank, u32 addr, u64 paddr, u32 size) in uniphier_system_bus_add_bank() argument
45 bank, addr, paddr, size); in uniphier_system_bus_add_bank()
47 if (bank >= ARRAY_SIZE(priv->bank)) { in uniphier_system_bus_add_bank()
48 dev_err(priv->dev, "unsupported bank number %d\n", bank); in uniphier_system_bus_add_bank()
52 if (priv->bank[bank].base || priv->bank[bank].end) { in uniphier_system_bus_add_bank()
54 "range for bank %d has already been specified\n", bank); in uniphier_system_bus_add_bank()
86 priv->bank[bank].base = paddr; in uniphier_system_bus_add_bank()
87 priv->bank[bank].end = end; in uniphier_system_bus_add_bank()
90 bank, priv->bank[bank].base, priv->bank[bank].end); in uniphier_system_bus_add_bank()
[all …]
|
| /linux-6.12.1/drivers/pinctrl/ |
| D | pinctrl-rockchip.c | 723 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, in rockchip_get_recalced_mux() argument
726 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
733 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
1070 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, in rockchip_get_mux_route() argument
1073 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1080 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1095 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) in rockchip_get_mux() argument
1097 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1108 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1113 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
[all …]
|
| /linux-6.12.1/drivers/leds/ |
| D | leds-tca6507.c | 159 struct bank { struct
164 } bank[3]; member
175 int bank; /* Bank used, or -1 */ member
278 static void set_code(struct tca6507_chip *tca, int reg, int bank, int new) in set_code() argument
282 if (bank) { in set_code()
295 static void set_level(struct tca6507_chip *tca, int bank, int level) in set_level() argument
297 switch (bank) { in set_level()
300 set_code(tca, TCA6507_MAX_INTENSITY, bank, level); in set_level()
306 tca->bank[bank].level = level; in set_level()
310 static void set_times(struct tca6507_chip *tca, int bank) in set_times() argument
[all …]
|
| /linux-6.12.1/sound/pci/au88x0/ |
| D | au88x0_wt.h | 21 #define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */ argument
22 #define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */ argument
23 #define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */ argument
24 #define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */ argument
25 #define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */ argument
26 #define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */ argument
|
| /linux-6.12.1/drivers/pinctrl/nuvoton/ |
| D | pinctrl-ma35.c | 335 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_direction_in() local
336 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE; in ma35_gpio_core_direction_in()
347 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_direction_out() local
348 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT; in ma35_gpio_core_direction_out()
349 void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE; in ma35_gpio_core_direction_out()
368 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_get() local
369 void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN; in ma35_gpio_core_get()
376 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_set() local
377 void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT; in ma35_gpio_core_set()
390 struct ma35_pin_bank *bank = gpiochip_get_data(gc); in ma35_gpio_core_to_request() local
[all …]
|