1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __NISLANDS_SMC_H__ 24 #define __NISLANDS_SMC_H__ 25 26 #pragma pack(push, 1) 27 28 #define NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 29 30 struct PP_NIslands_Dpm2PerfLevel { 31 uint8_t MaxPS; 32 uint8_t TgtAct; 33 uint8_t MaxPS_StepInc; 34 uint8_t MaxPS_StepDec; 35 uint8_t PSST; 36 uint8_t NearTDPDec; 37 uint8_t AboveSafeInc; 38 uint8_t BelowSafeInc; 39 uint8_t PSDeltaLimit; 40 uint8_t PSDeltaWin; 41 uint8_t Reserved[6]; 42 }; 43 44 typedef struct PP_NIslands_Dpm2PerfLevel PP_NIslands_Dpm2PerfLevel; 45 46 struct PP_NIslands_DPM2Parameters { 47 uint32_t TDPLimit; 48 uint32_t NearTDPLimit; 49 uint32_t SafePowerLimit; 50 uint32_t PowerBoostLimit; 51 }; 52 typedef struct PP_NIslands_DPM2Parameters PP_NIslands_DPM2Parameters; 53 54 struct NISLANDS_SMC_SCLK_VALUE { 55 uint32_t vCG_SPLL_FUNC_CNTL; 56 uint32_t vCG_SPLL_FUNC_CNTL_2; 57 uint32_t vCG_SPLL_FUNC_CNTL_3; 58 uint32_t vCG_SPLL_FUNC_CNTL_4; 59 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 60 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 61 uint32_t sclk_value; 62 }; 63 64 typedef struct NISLANDS_SMC_SCLK_VALUE NISLANDS_SMC_SCLK_VALUE; 65 66 struct NISLANDS_SMC_MCLK_VALUE { 67 uint32_t vMPLL_FUNC_CNTL; 68 uint32_t vMPLL_FUNC_CNTL_1; 69 uint32_t vMPLL_FUNC_CNTL_2; 70 uint32_t vMPLL_AD_FUNC_CNTL; 71 uint32_t vMPLL_AD_FUNC_CNTL_2; 72 uint32_t vMPLL_DQ_FUNC_CNTL; 73 uint32_t vMPLL_DQ_FUNC_CNTL_2; 74 uint32_t vMCLK_PWRMGT_CNTL; 75 uint32_t vDLL_CNTL; 76 uint32_t vMPLL_SS; 77 uint32_t vMPLL_SS2; 78 uint32_t mclk_value; 79 }; 80 81 typedef struct NISLANDS_SMC_MCLK_VALUE NISLANDS_SMC_MCLK_VALUE; 82 83 struct NISLANDS_SMC_VOLTAGE_VALUE { 84 uint16_t value; 85 uint8_t index; 86 uint8_t padding; 87 }; 88 89 typedef struct NISLANDS_SMC_VOLTAGE_VALUE NISLANDS_SMC_VOLTAGE_VALUE; 90 91 struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL { 92 uint8_t arbValue; 93 uint8_t ACIndex; 94 uint8_t displayWatermark; 95 uint8_t gen2PCIE; 96 uint8_t reserved1; 97 uint8_t reserved2; 98 uint8_t strobeMode; 99 uint8_t mcFlags; 100 uint32_t aT; 101 uint32_t bSP; 102 NISLANDS_SMC_SCLK_VALUE sclk; 103 NISLANDS_SMC_MCLK_VALUE mclk; 104 NISLANDS_SMC_VOLTAGE_VALUE vddc; 105 NISLANDS_SMC_VOLTAGE_VALUE mvdd; 106 NISLANDS_SMC_VOLTAGE_VALUE vddci; 107 NISLANDS_SMC_VOLTAGE_VALUE std_vddc; 108 uint32_t powergate_en; 109 uint8_t hUp; 110 uint8_t hDown; 111 uint8_t stateFlags; 112 uint8_t arbRefreshState; 113 uint32_t SQPowerThrottle; 114 uint32_t SQPowerThrottle_2; 115 uint32_t reserved[2]; 116 PP_NIslands_Dpm2PerfLevel dpm2; 117 }; 118 119 #define NISLANDS_SMC_STROBE_RATIO 0x0F 120 #define NISLANDS_SMC_STROBE_ENABLE 0x10 121 122 #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01 123 #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02 124 #define NISLANDS_SMC_MC_RTT_ENABLE 0x04 125 #define NISLANDS_SMC_MC_STUTTER_EN 0x08 126 127 typedef struct NISLANDS_SMC_HW_PERFORMANCE_LEVEL NISLANDS_SMC_HW_PERFORMANCE_LEVEL; 128 129 struct NISLANDS_SMC_SWSTATE { 130 uint8_t flags; 131 uint8_t levelCount; 132 uint8_t padding2; 133 uint8_t padding3; 134 NISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[]; 135 }; 136 137 typedef struct NISLANDS_SMC_SWSTATE NISLANDS_SMC_SWSTATE; 138 139 struct NISLANDS_SMC_SWSTATE_SINGLE { 140 uint8_t flags; 141 uint8_t levelCount; 142 uint8_t padding2; 143 uint8_t padding3; 144 NISLANDS_SMC_HW_PERFORMANCE_LEVEL level; 145 }; 146 147 #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0 148 #define NISLANDS_SMC_VOLTAGEMASK_MVDD 1 149 #define NISLANDS_SMC_VOLTAGEMASK_VDDCI 2 150 #define NISLANDS_SMC_VOLTAGEMASK_MAX 4 151 152 struct NISLANDS_SMC_VOLTAGEMASKTABLE { 153 uint8_t highMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 154 uint32_t lowMask[NISLANDS_SMC_VOLTAGEMASK_MAX]; 155 }; 156 157 typedef struct NISLANDS_SMC_VOLTAGEMASKTABLE NISLANDS_SMC_VOLTAGEMASKTABLE; 158 159 #define NISLANDS_MAX_NO_VREG_STEPS 32 160 161 struct NISLANDS_SMC_STATETABLE { 162 uint8_t thermalProtectType; 163 uint8_t systemFlags; 164 uint8_t maxVDDCIndexInPPTable; 165 uint8_t extraFlags; 166 uint8_t highSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 167 uint32_t lowSMIO[NISLANDS_MAX_NO_VREG_STEPS]; 168 NISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; 169 PP_NIslands_DPM2Parameters dpm2Params; 170 struct NISLANDS_SMC_SWSTATE_SINGLE initialState; 171 struct NISLANDS_SMC_SWSTATE_SINGLE ACPIState; 172 struct NISLANDS_SMC_SWSTATE_SINGLE ULVState; 173 NISLANDS_SMC_SWSTATE driverState; 174 NISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; 175 }; 176 177 typedef struct NISLANDS_SMC_STATETABLE NISLANDS_SMC_STATETABLE; 178 179 #define NI_SMC_SOFT_REGISTERS_START 0x108 180 181 #define NI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0 182 #define NI_SMC_SOFT_REGISTER_delay_bbias 0xC 183 #define NI_SMC_SOFT_REGISTER_delay_vreg 0x10 184 #define NI_SMC_SOFT_REGISTER_delay_acpi 0x2C 185 #define NI_SMC_SOFT_REGISTER_seq_index 0x64 186 #define NI_SMC_SOFT_REGISTER_mvdd_chg_time 0x68 187 #define NI_SMC_SOFT_REGISTER_mclk_switch_lim 0x78 188 #define NI_SMC_SOFT_REGISTER_watermark_threshold 0x80 189 #define NI_SMC_SOFT_REGISTER_mc_block_delay 0x84 190 #define NI_SMC_SOFT_REGISTER_uvd_enabled 0x98 191 192 #define SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES 16 193 #define SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 194 #define SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 195 #define SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES 4 196 197 struct SMC_NISLANDS_MC_TPP_CAC_TABLE { 198 uint32_t tpp[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES]; 199 uint32_t cacValue[SMC_NISLANDS_MC_TPP_CAC_NUM_OF_ENTRIES]; 200 }; 201 202 typedef struct SMC_NISLANDS_MC_TPP_CAC_TABLE SMC_NISLANDS_MC_TPP_CAC_TABLE; 203 204 205 struct PP_NIslands_CACTABLES { 206 uint32_t cac_bif_lut[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES]; 207 uint32_t cac_lkge_lut[SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES]; 208 209 uint32_t pwr_const; 210 211 uint32_t dc_cacValue; 212 uint32_t bif_cacValue; 213 uint32_t lkge_pwr; 214 215 uint8_t cac_width; 216 uint8_t window_size_p2; 217 218 uint8_t num_drop_lsb; 219 uint8_t padding_0; 220 221 uint32_t last_power; 222 223 uint8_t AllowOvrflw; 224 uint8_t MCWrWeight; 225 uint8_t MCRdWeight; 226 uint8_t padding_1[9]; 227 228 uint8_t enableWinAvg; 229 uint8_t numWin_TDP; 230 uint8_t l2numWin_TDP; 231 uint8_t WinIndex; 232 233 uint32_t dynPwr_TDP[4]; 234 uint32_t lkgePwr_TDP[4]; 235 uint32_t power_TDP[4]; 236 uint32_t avg_dynPwr_TDP; 237 uint32_t avg_lkgePwr_TDP; 238 uint32_t avg_power_TDP; 239 uint32_t lts_power_TDP; 240 uint8_t lts_truncate_n; 241 uint8_t padding_2[7]; 242 }; 243 244 typedef struct PP_NIslands_CACTABLES PP_NIslands_CACTABLES; 245 246 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE 32 247 #define SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 248 249 struct SMC_NIslands_MCRegisterAddress { 250 uint16_t s0; 251 uint16_t s1; 252 }; 253 254 typedef struct SMC_NIslands_MCRegisterAddress SMC_NIslands_MCRegisterAddress; 255 256 257 struct SMC_NIslands_MCRegisterSet { 258 uint32_t value[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 259 }; 260 261 typedef struct SMC_NIslands_MCRegisterSet SMC_NIslands_MCRegisterSet; 262 263 struct SMC_NIslands_MCRegisters { 264 uint8_t last; 265 uint8_t reserved[3]; 266 SMC_NIslands_MCRegisterAddress address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; 267 SMC_NIslands_MCRegisterSet data[SMC_NISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; 268 }; 269 270 typedef struct SMC_NIslands_MCRegisters SMC_NIslands_MCRegisters; 271 272 struct SMC_NIslands_MCArbDramTimingRegisterSet { 273 uint32_t mc_arb_dram_timing; 274 uint32_t mc_arb_dram_timing2; 275 uint8_t mc_arb_rfsh_rate; 276 uint8_t padding[3]; 277 }; 278 279 typedef struct SMC_NIslands_MCArbDramTimingRegisterSet SMC_NIslands_MCArbDramTimingRegisterSet; 280 281 struct SMC_NIslands_MCArbDramTimingRegisters { 282 uint8_t arb_current; 283 uint8_t reserved[3]; 284 SMC_NIslands_MCArbDramTimingRegisterSet data[20]; 285 }; 286 287 typedef struct SMC_NIslands_MCArbDramTimingRegisters SMC_NIslands_MCArbDramTimingRegisters; 288 289 struct SMC_NISLANDS_SPLL_DIV_TABLE { 290 uint32_t freq[256]; 291 uint32_t ss[256]; 292 }; 293 294 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff 295 #define SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0 296 #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000 297 #define SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25 298 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff 299 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0 300 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000 301 #define SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20 302 303 typedef struct SMC_NISLANDS_SPLL_DIV_TABLE SMC_NISLANDS_SPLL_DIV_TABLE; 304 305 #define NISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x100 306 307 #define NISLANDS_SMC_FIRMWARE_HEADER_version 0x0 308 #define NISLANDS_SMC_FIRMWARE_HEADER_flags 0x4 309 #define NISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0x8 310 #define NISLANDS_SMC_FIRMWARE_HEADER_stateTable 0xC 311 #define NISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x10 312 #define NISLANDS_SMC_FIRMWARE_HEADER_cacTable 0x14 313 #define NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20 314 #define NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x2C 315 #define NISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x30 316 317 #pragma pack(pop) 318 319 #endif 320 321