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Searched refs:ast_get_index_reg_mask (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/ast/
Dast_ddc.c50 jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x04); in ast_ddc_algo_bit_data_setsda()
66 jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x01); in ast_ddc_algo_bit_data_setscl()
102 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01; in ast_ddc_algo_bit_data_getsda()
104 val2 = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01; in ast_ddc_algo_bit_data_getsda()
109 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x20) >> 5) & 0x01; in ast_ddc_algo_bit_data_getsda()
124 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01; in ast_ddc_algo_bit_data_getscl()
126 val2 = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01; in ast_ddc_algo_bit_data_getscl()
131 val = (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x10) >> 4) & 0x01; in ast_ddc_algo_bit_data_getscl()
Dast_dp501.c39 sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff); in send_ack()
47 sendack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x9b, 0xff); in send_nack()
57 waitack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff); in wait_ack()
73 waitack = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff); in wait_nack()
100 waitready = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd2, 0xff);
161 tmp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd3, 0xff);
273 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */ in ast_launch_m68k()
360 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_init_dvo()
457 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff); in ast_init_3rdtx()
Dast_main.c49 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_detect_widescreen()
86 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff); in ast_detect_tx_chip()
97 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff); in ast_detect_tx_chip()
116 if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xD1, TX_TYPE_MASK) == in ast_detect_tx_chip()
Dast_mm.c42 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xaa, 0xff); in ast_get_vram_size()
58 jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0x99, 0xff); in ast_get_vram_size()
Dast_dp.c18 if (!ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, AST_IO_VGACRDF_HPD)) in ast_astdp_is_connected()
165 u8 bE3 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xE3, AST_DP_VIDEO_ENABLE); in ast_dp_power_on_off()
205 while (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xDF, in ast_dp_set_on_off()
Dast_post.c262 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_init_dram_reg()
342 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_init_dram_reg()
1579 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2300()
1651 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2300()
2047 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2500()
2095 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff); in ast_post_chip_2500()
Dast_drv.h323 static inline u8 ast_get_index_reg_mask(struct ast_device *ast, u32 base, u8 index, in ast_get_index_reg_mask() function
Dast_mode.c1049 jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff); in ast_crtc_helper_mode_valid()