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/linux-6.12.1/drivers/clk/mediatek/
Dclk-mux.h41 #define __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \ argument
55 .parent_names = _parents, \
62 #define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
65 __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
66 NULL, ARRAY_SIZE(_parents), _mux_ofs, \
70 #define GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, _paridx, \ argument
73 __GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
81 #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ argument
84 GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
89 #define MUX_GATE_CLR_SET_UPD_FLAGS_INDEXED(_id, _name, _parents, \ argument
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Dclk-mtk.h112 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
122 .parent_names = _parents, \
123 .num_parents = ARRAY_SIZE(_parents), \
132 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
134 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
141 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
142 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
145 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
146 MUX_FLAGS(_id, _name, _parents, _reg, \
149 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
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Dclk-mt6795-topckgen.c21 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
22 MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \
26 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
27 TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
Dclk-mt8173-topckgen.c22 #define TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
23 MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _reg, \
27 #define TOP_MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) \ argument
28 TOP_MUX_GATE_NOSR(_id, _name, _parents, _reg, _shift, _width, \
/linux-6.12.1/drivers/clk/sunxi-ng/
Dccu_mux.h49 #define SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, _table, \ argument
58 _parents, \
65 #define SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(_struct, _name, _parents, \ argument
68 SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, \
73 #define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \ argument
76 SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, \
80 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
82 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
86 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
88 SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, NULL, \
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Dccu_mp.h34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
49 _parents, \
55 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
68 _parents, \
74 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
79 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
85 #define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
98 _parents, \
104 #define SUNXI_CCU_MP_DATA_WITH_MUX(_struct, _name, _parents, _reg, \ argument
109 SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
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Dccu_div.h128 _parents, _table, \ argument
140 _parents, \
147 _parents, _table, \ argument
159 _parents, \
166 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
170 _parents, NULL, \
175 #define SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(_struct, _name, _parents, \ argument
180 _parents, NULL, \
185 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
189 _parents, NULL, \
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Dccu_nkm.h36 #define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \ argument
52 _parents, \
/linux-6.12.1/drivers/clk/sprd/
Dmux.h39 #define SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \ argument
46 .hw.init = _fn(_name, _parents, \
51 #define SPRD_MUX_CLK_TABLE(_struct, _name, _parents, _table, \ argument
53 SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument
59 SPRD_MUX_CLK_TABLE(_struct, _name, _parents, NULL, \
62 #define SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, _table, \ argument
64 SPRD_MUX_CLK_HW_INIT_FN(_struct, _name, _parents, _table, \
68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument
70 SPRD_MUX_CLK_DATA_TABLE(_struct, _name, _parents, NULL, \
/linux-6.12.1/drivers/clk/tegra/
Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
134 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
136 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
141 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
143 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\
146 #define MUX8(_name, _parents, _offset, \ argument
148 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
150 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
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Dclk-tegra30.c157 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
159 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
163 #define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \ argument
165 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
169 #define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \ argument
171 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
176 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
179 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
Dclk-tegra20.c135 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ argument
137 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
142 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \ argument
144 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
149 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \ argument
152 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
Dclk-tegra124.c97 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
98 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
101 _parents##_idx, 0, _lock)
103 #define NODIV(_name, _parents, _offset, \ argument
106 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
109 _clk_id, _parents##_idx, 0, _lock)
Dclk-tegra114.c115 #define MUX8(_name, _parents, _offset, \ argument
117 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
119 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
/linux-6.12.1/drivers/clk/pxa/
Dclk-pxa.h18 static const char *const name ## _parents[] __initconst
32 name ## _parents, \
33 ARRAY_SIZE(name ## _parents), \
47 name ## _parents, \
48 ARRAY_SIZE(name ## _parents), \
64 name ## _parents, \
65 ARRAY_SIZE(name ## _parents), \
81 name ## _parents, \
82 ARRAY_SIZE(name ## _parents), \
/linux-6.12.1/drivers/clk/actions/
Dowl-mux.h34 #define OWL_MUX(_struct, _name, _parents, _reg, \ argument
41 _parents, \
/linux-6.12.1/drivers/clk/microchip/
Dclk-mpfs-ccc.c101 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ argument
107 .parents = _parents, \
187 #define CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(_name, _parents, _ops, _flags) \ argument
191 .parent_data = _parents, \
/linux-6.12.1/drivers/clk/sophgo/
Dclk-cv18xx-common.h20 #define CV1800_CLK_COMMON(_name, _parents, _op, _flags) \ argument
22 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parents, \
Dclk-sg2042-clkgen.c409 #define SG2042_MUX(_id, _name, _parents, _flags, _r_select, _shift, _width) { \ argument
413 _parents, \
/linux-6.12.1/include/linux/
Dclk-provider.h1487 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \ argument
1491 .parent_names = _parents, \
1492 .num_parents = ARRAY_SIZE(_parents), \
1496 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \ argument
1500 .parent_hws = _parents, \
1501 .num_parents = ARRAY_SIZE(_parents), \
1505 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \ argument
1509 .parent_data = _parents, \
1510 .num_parents = ARRAY_SIZE(_parents), \
Dsh_clk.h175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument
182 .parent_table = _parents, \
/linux-6.12.1/drivers/clk/
Dclk-stm32h7.c567 #define M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, _flags)\ argument
570 .parents = _parents,\
571 .num_parents = ARRAY_SIZE(_parents),\
578 #define M_MCLOC(_name, _parents, _mux_offset, _mux_shift, _mux_width)\ argument
579 M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, 0)\
1177 #define M_MCO_F(_name, _parents, _mux_offset, _mux_shift, _mux_width,\ argument
1185 .parent_name = _parents,\
1186 .num_parents = ARRAY_SIZE(_parents),\
Dclk-bm1880.c160 #define GATE_MUX(_id, _name, _parents, _gate_reg, _gate_shift, \ argument
163 .parents = _parents, \
164 .num_parents = ARRAY_SIZE(_parents), \
/linux-6.12.1/drivers/clk/stm32/
Dclk-stm32mp1.c1218 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument
1222 .parent_names = _parents,\
1223 .num_parents = ARRAY_SIZE(_parents),\
1234 #define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\ argument
1238 .parent_names = _parents,\
1239 .num_parents = ARRAY_SIZE(_parents),\
1368 #define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\ argument
1372 .parent_names = _parents,\
1373 .num_parents = ARRAY_SIZE(_parents),\
1389 #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\ argument
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/linux-6.12.1/drivers/clk/meson/
Daxg-audio.c322 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents) \ argument
323 AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents, \