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/linux-6.12.1/drivers/thermal/qcom/
Dtsens.h88 #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ argument
89 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \
90 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \
91 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \
92 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \
93 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \
94 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \
95 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \
96 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \
97 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \
[all …]
/linux-6.12.1/drivers/clk/bcm/
Dclk-kona.h91 #define POLICY(_offset, _bit) \ argument
93 .offset = (_offset), \
151 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
153 .offset = (_offset), \
163 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
165 .offset = (_offset), \
174 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
176 .offset = (_offset), \
185 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
187 .offset = (_offset), \
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlxsw/
Dcore_acl_flex_keys.h56 #define MLXSW_AFK_ELEMENT_INFO(_type, _element, _offset, _shift, _size) \ argument
61 .offset = _offset, \
68 #define MLXSW_AFK_ELEMENT_INFO_U32(_element, _offset, _shift, _size) \ argument
70 _element, _offset, _shift, _size)
72 #define MLXSW_AFK_ELEMENT_INFO_BUF(_element, _offset, _size) \ argument
74 _element, _offset, 0, _size)
88 #define MLXSW_AFK_ELEMENT_INST(_type, _element, _offset, \ argument
94 .offset = _offset, \
103 #define MLXSW_AFK_ELEMENT_INST_U32(_element, _offset, _shift, _size) \ argument
105 _element, _offset, _shift, _size, 0, false)
[all …]
Ditem.h270 #define MLXSW_ITEM8(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
272 .offset = _offset, \
288 #define MLXSW_ITEM8_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
291 .offset = _offset, \
313 #define MLXSW_ITEM16(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
315 .offset = _offset, \
331 #define MLXSW_ITEM16_INDEXED(_type, _cname, _iname, _offset, _shift, _sizebits, \ argument
334 .offset = _offset, \
356 #define MLXSW_ITEM32(_type, _cname, _iname, _offset, _shift, _sizebits) \ argument
358 .offset = _offset, \
[all …]
/linux-6.12.1/drivers/clk/tegra/
Dclk-tegra-periph.c132 #define MUX(_name, _parents, _offset, \ argument
134 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
139 #define MUX_FLAGS(_name, _parents, _offset,\ argument
141 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
146 #define MUX8(_name, _parents, _offset, \ argument
148 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
153 #define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ argument
154 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
159 #define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \ argument
160 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
[all …]
Dclk-tegra-audio.c52 #define AUDIO(_name, _offset) \ argument
56 .offset = _offset,\
71 #define AUDIO2X(_name, _num, _offset) \ argument
79 .div_offset = _offset,\
/linux-6.12.1/drivers/clk/renesas/
Drcar-gen4-cpg.h35 #define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ argument
36 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
38 #define DEF_GEN4_SD(_name, _id, _parent, _offset) \ argument
39 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
61 #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ argument
62 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
Drcar-gen3-cpg.h37 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ argument
38 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset)
40 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
41 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
60 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
61 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
Drenesas-cpg-mssr.h53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
56 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
/linux-6.12.1/drivers/clk/sunxi-ng/
Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
21 .offset = _offset, \
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
/linux-6.12.1/drivers/pinctrl/mediatek/
Dpinctrl-mtk-common.h109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
112 .offset = _offset, \
134 #define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \ argument
137 .offset = _offset, \
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
162 .offset = _offset, \
/linux-6.12.1/drivers/clk/sprd/
Ddiv.h28 #define _SPRD_DIV_CLK(_offset, _shift, _width) \ argument
30 .offset = _offset, \
40 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _offset, \ argument
43 .div = _SPRD_DIV_CLK(_offset, _shift, _width), \
/linux-6.12.1/drivers/bcma/
Dsprom.c185 #define SPEX(_field, _offset, _mask, _shift) \ argument
186 bus->sprom._field = ((sprom[SPOFF(_offset)] & (_mask)) >> (_shift))
188 #define SPEX32(_field, _offset, _mask, _shift) \ argument
189 bus->sprom._field = ((((u32)sprom[SPOFF((_offset)+2)] << 16 | \
190 sprom[SPOFF(_offset)]) & (_mask)) >> (_shift))
192 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
194 SPEX(_field[0], _offset + 0, _mask, _shift); \
195 SPEX(_field[1], _offset + 2, _mask, _shift); \
196 SPEX(_field[2], _offset + 4, _mask, _shift); \
197 SPEX(_field[3], _offset + 6, _mask, _shift); \
[all …]
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt6795-apmixedsys.c76 #define _FH(_pllid, _fhid, _slope, _offset) { \ argument
81 .fhx_offset = _offset, \
99 #define FH(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6003c97, _offset) argument
100 #define FH_M(_pllid, _fhid, _offset) _FH(_pllid, _fhid, 0x6000140, _offset) argument
/linux-6.12.1/fs/bcachefs/
Dbcachefs.h252 #define bch2_fmt_dev_offset(_ca, _offset, fmt) "bcachefs (%s sector %llu): " fmt "\n", ((_ca)->name… argument
254 #define bch2_fmt_inum_offset(_c, _inum, _offset, fmt) \ argument
255 "bcachefs (%s inum %llu offset %llu): " fmt "\n", ((_c)->name), (_inum), (_offset)
261 #define bch2_fmt_dev_offset(_ca, _offset, fmt) "%s sector %llu: " fmt "\n", ((_ca)->name), (_offset) argument
263 #define bch2_fmt_inum_offset(_c, _inum, _offset, fmt) \ argument
264 "inum %llu offset %llu: " fmt "\n", (_inum), (_offset)
307 #define bch_err_dev_offset(ca, _offset, fmt, ...) \ argument
308 bch2_print(c, KERN_ERR bch2_fmt_dev_offset(ca, _offset, fmt), ##__VA_ARGS__)
311 #define bch_err_inum_offset(c, _inum, _offset, fmt, ...) \ argument
312 bch2_print(c, KERN_ERR bch2_fmt_inum_offset(c, _inum, _offset, fmt), ##__VA_ARGS__)
[all …]
/linux-6.12.1/drivers/clk/
Dclk-loongson2.c59 #define CLK_DIV(_id, _name, _pname, _offset, _dshift, _dwidth) \ argument
65 .reg_offset = _offset, \
70 #define CLK_PLL(_id, _name, _offset, _mshift, _mwidth, \ argument
77 .reg_offset = _offset, \
84 #define CLK_SCALE(_id, _name, _pname, _offset, \ argument
91 .reg_offset = _offset, \
96 #define CLK_GATE(_id, _name, _pname, _offset, _bidx) \ argument
102 .reg_offset = _offset, \
/linux-6.12.1/arch/riscv/include/asm/
Dvdso.h23 (void __user *)((unsigned long)(base) + __vdso_##name##_offset)
29 (void __user *)((unsigned long)(base) + compat__vdso_##name##_offset)
/linux-6.12.1/tools/testing/selftests/powerpc/nx-gzip/include/
Dnxu.h428 #define getnn(ST, REG) ((be32toh(ST.REG) >> (31-REG##_offset)) \
430 #define getpnn(ST, REG) ((be32toh((ST)->REG) >> (31-REG##_offset)) \
438 << (31-REG##_offset)))
442 << (31-REG##_offset)))
453 & REG##_mask) << (31-REG##_offset))))
455 | (((X) & REG##_mask) << (31-REG##_offset))))
/linux-6.12.1/drivers/ssb/
Dpci.c171 #define SPEX16(_outvar, _offset, _mask, _shift) \ argument
172 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
173 #define SPEX32(_outvar, _offset, _mask, _shift) \ argument
174 out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
175 in[SPOFF(_offset)]) & (_mask)) >> (_shift))
176 #define SPEX(_outvar, _offset, _mask, _shift) \ argument
177 SPEX16(_outvar, _offset, _mask, _shift)
179 #define SPEX_ARRAY8(_field, _offset, _mask, _shift) \ argument
181 SPEX(_field[0], _offset + 0, _mask, _shift); \
182 SPEX(_field[1], _offset + 2, _mask, _shift); \
[all …]
/linux-6.12.1/drivers/pinctrl/berlin/
Dberlin.h31 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
34 .offset = _offset, \
/linux-6.12.1/drivers/clk/st/
Dclkgen.h38 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ argument
39 .offset = _offset, \
/linux-6.12.1/drivers/clk/microchip/
Dclk-mpfs.c136 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ argument
141 .reg_offset = _offset, \
175 #define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \ argument
180 .reg_offset = _offset, \
223 #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ argument
228 .reg_offset = _offset, \
Dclk-mpfs-ccc.c101 #define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \ argument
105 .reg_offset = _offset, \
124 #define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \ argument
128 .reg_offset = _offset, \
/linux-6.12.1/arch/powerpc/boot/
Dlibfdt-wrapper.c33 unsigned long _offset = (off); \
34 check_err(_offset) ? NULL : (void *)(_offset+1); \
/linux-6.12.1/tools/objtool/include/objtool/
Delf.h327 #define for_offset_range(_offset, _start, _end) \ argument
328 for (_offset = ((_start) & OFFSET_STRIDE_MASK); \
329 _offset >= ((_start) & OFFSET_STRIDE_MASK) && \
330 _offset <= ((_end) & OFFSET_STRIDE_MASK); \
331 _offset += OFFSET_STRIDE)

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