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Searched refs:__raw_writel (Results 1 – 25 of 426) sorted by relevance

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/linux-6.12.1/arch/mips/alchemy/common/
Dirq.c293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic0_unmask()
303 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic1_unmask()
313 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_mask()
323 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic1_mask()
324 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic1_mask()
337 __raw_writel(1 << bit, base + IC_FALLINGCLR); in au1x_ic0_ack()
338 __raw_writel(1 << bit, base + IC_RISINGCLR); in au1x_ic0_ack()
[all …]
Dusb.c112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
128 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
134 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
141 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
145 __raw_writel(0, base + USB_DWC_CTRL7); in __au1300_ohci_control()
150 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
156 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
170 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ehci_control()
175 __raw_writel(r, base + USB_DWC_CTRL1); in __au1300_ehci_control()
[all …]
Dvss.c27 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ in __enable_block()
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
49 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ in __enable_block()
58 __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */ in __disable_block()
[all …]
/linux-6.12.1/arch/mips/kernel/
Dcevt-txx9.c63 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
64 __raw_writel(0, &tmrptr->tisr); in txx9_clocksource_init()
65 __raw_writel(TIMER_CCD, &tmrptr->ccdr); in txx9_clocksource_init()
66 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9_clocksource_init()
67 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); in txx9_clocksource_init()
68 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_clocksource_init()
83 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9tmr_stop_and_clear()
85 __raw_writel(0, &tmrptr->tisr); in txx9tmr_stop_and_clear()
96 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9tmr_set_state_periodic()
98 __raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> evt->shift, in txx9tmr_set_state_periodic()
[all …]
/linux-6.12.1/arch/arm/mach-mmp/
Dtime.c50 __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); in timer_read()
70 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_interrupt()
75 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_interrupt()
92 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_set_next_event()
97 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_set_next_event()
98 __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); in timer_set_next_event()
103 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); in timer_set_next_event()
108 __raw_writel(0x03, mmp_timer_base + TMR_CER); in timer_set_next_event()
121 __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); in timer_set_shutdown()
153 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */ in timer_config()
[all …]
/linux-6.12.1/arch/mips/sgi-ip22/
Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
64 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
[all …]
/linux-6.12.1/arch/mips/pci/
Dops-tx4927.c64 __raw_writel(((bus->number & 0xff) << 0x10) in mkaddr()
69 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
84 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
130 __raw_writel(val, &pcicptr->g2pcfgdata); in icd_writel()
243 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
251 __raw_writel((channel->io_resource->end - channel->io_resource->start) in tx4927_pcic_setup()
265 __raw_writel(0, &pcicptr->g2pmmask[i]); in tx4927_pcic_setup()
270 __raw_writel((channel->mem_resource->end in tx4927_pcic_setup()
285 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ in tx4927_pcic_setup()
288 __raw_writel(0, &pcicptr->p2gm0plbase); in tx4927_pcic_setup()
[all …]
/linux-6.12.1/arch/sh/drivers/pci/
Dpci-sh7780.c127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
154 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
200 __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \ in sh7780_pci_setup_irqs()
205 __raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \ in sh7780_pci_setup_irqs()
231 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
241 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
258 __raw_writel(PCIECR_ENBL, PCIECR); in sh7780_pci_init()
261 __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST | PCICR_ENDIANNESS, in sh7780_pci_init()
[all …]
/linux-6.12.1/arch/mips/loongson32/common/
Dirq.c28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
70 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
76 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n)) in ls1x_irq_settype()
80 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
[all …]
/linux-6.12.1/sound/soc/au1x/
Dpsc-ac97.c78 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_read()
85 __raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg), in au1xpsc_ac97_read()
98 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_read()
118 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_write()
125 __raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff), in au1xpsc_ac97_write()
136 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_write()
148 __raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata)); in au1xpsc_ac97_warm_reset()
151 __raw_writel(0, AC97_RST(pscdata)); in au1xpsc_ac97_warm_reset()
161 __raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata)); in au1xpsc_ac97_cold_reset()
163 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata)); in au1xpsc_ac97_cold_reset()
[all …]
Dpsc-i2s.c149 __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata)); in au1xpsc_i2s_configure()
159 __raw_writel(0, I2S_CFG(pscdata)); in au1xpsc_i2s_configure()
161 __raw_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata)); in au1xpsc_i2s_configure()
173 __raw_writel(0, I2S_CFG(pscdata)); in au1xpsc_i2s_configure()
174 __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata)); in au1xpsc_i2s_configure()
194 __raw_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata)); in au1xpsc_i2s_start()
196 __raw_writel(I2SPCR_START(stype), I2S_PCR(pscdata)); in au1xpsc_i2s_start()
205 __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); in au1xpsc_i2s_start()
217 __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); in au1xpsc_i2s_stop()
228 __raw_writel(0, I2S_CFG(pscdata)); in au1xpsc_i2s_stop()
[all …]
/linux-6.12.1/arch/m68k/coldfire/
Dpci.c71 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_readconfig()
87 __raw_writel(0, PCICAR); in mcf_pci_readconfig()
103 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_writeconfig()
115 __raw_writel(cpu_to_le32(value), addr); in mcf_pci_writeconfig()
119 __raw_writel(0, PCICAR); in mcf_pci_writeconfig()
178 __raw_writel(PCIGSCR_RESET, PCIGSCR); in mcf_pci_init()
179 __raw_writel(0, PCITCR); in mcf_pci_init()
185 __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) | in mcf_pci_init()
193 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | in mcf_pci_init()
195 __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1); in mcf_pci_init()
[all …]
/linux-6.12.1/arch/arm/mach-pxa/
Dsmemc.c37 __raw_writel(msc[0], MSC0); in pxa3xx_smemc_resume()
38 __raw_writel(msc[1], MSC1); in pxa3xx_smemc_resume()
39 __raw_writel(sxcnfg, SXCNFG); in pxa3xx_smemc_resume()
40 __raw_writel(memclkcfg, MEMCLKCFG); in pxa3xx_smemc_resume()
41 __raw_writel(csadrcfg[0], CSADRCFG0); in pxa3xx_smemc_resume()
42 __raw_writel(csadrcfg[1], CSADRCFG1); in pxa3xx_smemc_resume()
43 __raw_writel(csadrcfg[2], CSADRCFG2); in pxa3xx_smemc_resume()
44 __raw_writel(csadrcfg[3], CSADRCFG3); in pxa3xx_smemc_resume()
46 __raw_writel(0x2, CSMSADRCFG); in pxa3xx_smemc_resume()
65 __raw_writel(0x2, CSMSADRCFG); in smemc_init()
/linux-6.12.1/arch/sh/mm/
Dtlb-pteaex.c32 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
35 __raw_writel(get_asid(), MMU_PTEAEX); in __update_tlb()
47 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
56 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
73 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
74 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
75 __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
76 __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
98 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
101 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
Dtlb-sh4.c30 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
42 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
48 __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA); in __update_tlb()
58 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
78 __raw_writel(data, addr); in local_flush_tlb_one()
100 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
103 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
/linux-6.12.1/arch/sh/kernel/cpu/sh4a/
Dubc.c34 __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx)); in sh4a_ubc_enable()
35 __raw_writel(info->address, UBC_CAR(idx)); in sh4a_ubc_enable()
40 __raw_writel(0, UBC_CBR(idx)); in sh4a_ubc_disable()
41 __raw_writel(0, UBC_CAR(idx)); in sh4a_ubc_disable()
50 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
59 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
82 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
112 __raw_writel(0, UBC_CBCR); in sh4a_ubc_init()
115 __raw_writel(0, UBC_CAMR(i)); in sh4a_ubc_init()
116 __raw_writel(0, UBC_CBR(i)); in sh4a_ubc_init()
[all …]
Dsmp-shx3.c36 __raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */ in ipi_interrupt_handler()
51 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_smp_setup()
87 __raw_writel(entry_point, RESET_REG(cpu)); in shx3_start_cpu()
89 __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu)); in shx3_start_cpu()
92 __raw_writel(STBCR_MSTP, STBCR_REG(cpu)); in shx3_start_cpu()
98 __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_start_cpu()
112 __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */ in shx3_send_ipi()
117 __raw_writel(STBCR_MSTP, STBCR_REG(cpu)); in shx3_update_boot_vector()
120 __raw_writel(STBCR_RESET, STBCR_REG(cpu)); in shx3_update_boot_vector()
/linux-6.12.1/arch/mips/include/asm/mach-au1x00/
Dau1000_dma.h159 __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET); in enable_dma_buffer0()
168 __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffer1()
176 __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffers()
185 __raw_writel(DMA_GO, chan->io + DMA_MODE_SET); in start_dma()
197 __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); in halt_dma()
217 __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); in disable_dma()
241 __raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR); in init_dma()
247 __raw_writel(~mode, chan->io + DMA_MODE_CLEAR); in init_dma()
248 __raw_writel(mode, chan->io + DMA_MODE_SET); in init_dma()
306 __raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR); in set_dma_fifo_addr()
[all …]
/linux-6.12.1/arch/arm/mach-lpc32xx/
Dserial.c110 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); in lpc32xx_serial_init()
117 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
118 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
123 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
127 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); in lpc32xx_serial_init()
131 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
132 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
136 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
142 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
147 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
/linux-6.12.1/arch/mips/ath79/
Dcommon.c61 __raw_writel(0x1, flush_reg); in ath79_ddr_wb_flush()
66 __raw_writel(0x1, flush_reg); in ath79_ddr_wb_flush()
76 __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0); in ath79_ddr_set_pci_windows()
77 __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4); in ath79_ddr_set_pci_windows()
78 __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8); in ath79_ddr_set_pci_windows()
79 __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc); in ath79_ddr_set_pci_windows()
80 __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10); in ath79_ddr_set_pci_windows()
81 __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14); in ath79_ddr_set_pci_windows()
82 __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18); in ath79_ddr_set_pci_windows()
83 __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c); in ath79_ddr_set_pci_windows()
/linux-6.12.1/drivers/clocksource/
Dtimer-vf-pit.c38 __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL); in pit_timer_enable()
43 __raw_writel(0, clkevt_base + PITTCTRL); in pit_timer_disable()
48 __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); in pit_irq_acknowledge()
59 __raw_writel(0, clksrc_base + PITTCTRL); in pit_clocksource_init()
60 __raw_writel(~0UL, clksrc_base + PITLDVAL); in pit_clocksource_init()
61 __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); in pit_clocksource_init()
79 __raw_writel(delta - 1, clkevt_base + PITLDVAL); in pit_set_next_event()
128 __raw_writel(0, clkevt_base + PITTCTRL); in pit_clockevent_init()
129 __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); in pit_clockevent_init()
186 __raw_writel(~PITMCR_MDIS, timer_base + PITMCR); in pit_timer_init()
Dmxs_timer.c70 __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base + in timrot_irq_disable()
76 __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base + in timrot_irq_enable()
82 __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base + in timrot_irq_acknowledge()
96 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0)); in timrotv1_set_next_event()
105 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0)); in timrotv2_set_next_event()
127 __raw_writel(0xffff, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1)); in mxs_irq_clear()
129 __raw_writel(0xffffffff, in mxs_irq_clear()
234 __raw_writel((timrot_is_v1() ? in mxs_timer_init()
242 __raw_writel((timrot_is_v1() ? in mxs_timer_init()
250 __raw_writel(0xffff, in mxs_timer_init()
[all …]
/linux-6.12.1/drivers/watchdog/
Dixp4xx_wdt.c55 __raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET); in ixp4xx_wdt_start()
56 __raw_writel(0, iwdt->base + IXP4XX_OSWE_OFFSET); in ixp4xx_wdt_start()
57 __raw_writel(wdd->timeout * iwdt->rate, in ixp4xx_wdt_start()
59 __raw_writel(IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE, in ixp4xx_wdt_start()
61 __raw_writel(0, iwdt->base + IXP4XX_OSWK_OFFSET); in ixp4xx_wdt_start()
70 __raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET); in ixp4xx_wdt_stop()
71 __raw_writel(0, iwdt->base + IXP4XX_OSWE_OFFSET); in ixp4xx_wdt_stop()
72 __raw_writel(0, iwdt->base + IXP4XX_OSWK_OFFSET); in ixp4xx_wdt_stop()
92 __raw_writel(IXP4XX_WDT_KEY, iwdt->base + IXP4XX_OSWK_OFFSET); in ixp4xx_wdt_restart()
93 __raw_writel(0, iwdt->base + IXP4XX_OSWT_OFFSET); in ixp4xx_wdt_restart()
[all …]
/linux-6.12.1/arch/sh/kernel/cpu/sh3/
Dprobe.c31 __raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0); in cpu_probe()
33 __raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1); in cpu_probe()
38 __raw_writel(data0, addr0); in cpu_probe()
41 __raw_writel(data2, addr1); in cpu_probe()
45 __raw_writel(data0&~SH_CACHE_VALID, addr0); in cpu_probe()
46 __raw_writel(data2&~SH_CACHE_VALID, addr1); in cpu_probe()
94 __raw_writel(CCR_CACHE_32KB, CCR3_REG); in cpu_probe()
96 __raw_writel(CCR_CACHE_16KB, CCR3_REG); in cpu_probe()
/linux-6.12.1/drivers/soc/ixp4xx/
Dixp4xx-qmgr.c37 __raw_writel(val, &qmgr_regs->acc[queue][0]); in qmgr_put_entry()
129 __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), in qmgr_set_irq()
147 __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]); in qmgr_irq1_a0()
172 __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]); in qmgr_irq2_a0()
193 __raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */ in qmgr_irq()
212 __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask, in qmgr_enable_irq()
224 __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask, in qmgr_disable_irq()
226 __raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */ in qmgr_disable_irq()
313 __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]); in qmgr_request_queue()
363 __raw_writel(0, &qmgr_regs->sram[queue]); in qmgr_release_queue()
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