Home
last modified time | relevance | path

Searched refs:__DML2_WRAPPER_MAX_STREAMS_PLANES__ (Results 1 – 9 of 9) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/
Ddml2_internal_types.h69 #define __DML2_WRAPPER_MAX_STREAMS_PLANES__ 6 macro
72 unsigned int disp_cfg_to_stream_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
73 bool disp_cfg_to_stream_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
74 unsigned int disp_cfg_to_plane_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
75 bool disp_cfg_to_plane_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
76 unsigned int dml_pipe_idx_to_stream_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
77 bool dml_pipe_idx_to_stream_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
78 unsigned int dml_pipe_idx_to_plane_id[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
79 bool dml_pipe_idx_to_plane_id_valid[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
80 unsigned int dml_pipe_idx_to_plane_index[__DML2_WRAPPER_MAX_STREAMS_PLANES__];
[all …]
Ddml2_dc_resource_mgmt.c86 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in find_disp_cfg_idx_by_plane_id()
92 return __DML2_WRAPPER_MAX_STREAMS_PLANES__; in find_disp_cfg_idx_by_plane_id()
99 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in find_disp_cfg_idx_by_stream_id()
105 return __DML2_WRAPPER_MAX_STREAMS_PLANES__; in find_disp_cfg_idx_by_stream_id()
1054 …signed int odm_mode_array[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}, dpp_per_surface_array[__DML2… in dml2_map_dc_pipes()
1068 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml2_map_dc_pipes()
1075 disp_cfg_index_max = __DML2_WRAPPER_MAX_STREAMS_PLANES__; in dml2_map_dc_pipes()
Ddml2_translation_helper.c1095 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in map_stream_to_dml_display_cfg()
1141 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in map_plane_to_dml_display_cfg()
1174 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml2_populate_pipe_to_plane_index_mapping()
1179 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml2_populate_pipe_to_plane_index_mapping()
1272 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in map_dc_state_into_dml_display_cfg()
1306 …(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__); in map_dc_state_into_dml_display_cfg()
1346 …RT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__); in map_dc_state_into_dml_display_cfg()
Ddml2_utils.c197 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml2_helper_find_dml_pipe_idx_by_stream_id()
208 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in find_dml_pipe_idx_by_plane_id()
Ddml2_wrapper.c80 if (i >= __DML2_WRAPPER_MAX_STREAMS_PLANES__) { in map_hw_resources()
82 __func__, i, __DML2_WRAPPER_MAX_STREAMS_PLANES__); in map_hw_resources()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/
Ddml21_utils.h36 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],
37 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__],
Ddml21_utils.c17 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml21_helper_find_dml_pipe_idx_by_stream_id()
28 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml21_find_dml_pipe_idx_by_plane_id()
64 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in find_valid_pipe_idx_for_stream_index()
87 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__], in dml21_find_dc_pipes_for_plane() argument
88 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__], in dml21_find_dc_pipes_for_plane() argument
102 memset(dc_main_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__); in dml21_find_dc_pipes_for_plane()
103 memset(dc_phantom_pipes, 0, sizeof(struct pipe_ctx *) * __DML2_WRAPPER_MAX_STREAMS_PLANES__); in dml21_find_dc_pipes_for_plane()
Ddml21_wrapper.c125 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; in dml21_calculate_rq_and_dlg_params()
126 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; in dml21_calculate_rq_and_dlg_params()
292 struct pipe_ctx *dc_main_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__]; in dml21_prepare_mcache_programming()
293 struct pipe_ctx *dc_phantom_pipes[__DML2_WRAPPER_MAX_STREAMS_PLANES__] = {0}; in dml21_prepare_mcache_programming()
Ddml21_translation_helper.c891 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in map_stream_to_dml21_display_cfg()
913 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in map_plane_to_dml21_display_cfg()
974 …(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__); in dml21_map_dc_state_into_dml_display_cfg()
998 …RT(disp_cfg_plane_location >= 0 && disp_cfg_plane_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__); in dml21_map_dc_state_into_dml_display_cfg()
1157 for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { in dml21_map_hw_resources()