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Searched refs:XTFPGA_CLKFRQ_VADDR (Results 1 – 3 of 3) sorted by relevance

/linux-6.12.1/arch/xtensa/platforms/xtfpga/
Dsetup.c67 ccount_freq = *(long *)XTFPGA_CLKFRQ_VADDR; in platform_calibrate_ccount()
282 serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR; in xtavnet_init()
292 ethoc_pdata.eth_clkfreq = *(long *)XTFPGA_CLKFRQ_VADDR; in xtavnet_init()
/linux-6.12.1/arch/xtensa/platforms/xtfpga/include/platform/
Dserial.h16 #define BASE_BAUD (*(long *)XTFPGA_CLKFRQ_VADDR / 16)
Dhardware.h42 #define XTFPGA_CLKFRQ_VADDR (XTFPGA_FPGAREGS_VADDR + 0x04) macro