1  /*
2   * This file is provided under a dual BSD/GPLv2 license.  When using or
3   *   redistributing this file, you may do so under either license.
4   *
5   *   GPL LICENSE SUMMARY
6   *
7   *   Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
8   *
9   *   This program is free software; you can redistribute it and/or modify
10   *   it under the terms of version 2 of the GNU General Public License as
11   *   published by the Free Software Foundation.
12   *
13   *   BSD LICENSE
14   *
15   *   Copyright(c) 2012-2017 Intel Corporation. All rights reserved.
16   *
17   *   Redistribution and use in source and binary forms, with or without
18   *   modification, are permitted provided that the following conditions
19   *   are met:
20   *
21   *     * Redistributions of source code must retain the above copyright
22   *       notice, this list of conditions and the following disclaimer.
23   *     * Redistributions in binary form must reproduce the above copy
24   *       notice, this list of conditions and the following disclaimer in
25   *       the documentation and/or other materials provided with the
26   *       distribution.
27   *     * Neither the name of Intel Corporation nor the names of its
28   *       contributors may be used to endorse or promote products derived
29   *       from this software without specific prior written permission.
30   *
31   *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
32   *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
33   *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
34   *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
35   *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
36   *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
37   *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38   *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39   *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40   *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
41   *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42   */
43  
44  #ifndef _NTB_INTEL_GEN1_H_
45  #define _NTB_INTEL_GEN1_H_
46  
47  #include "ntb_hw_intel.h"
48  
49  /* Intel Gen1 Xeon hardware */
50  #define XEON_PBAR23LMT_OFFSET		0x0000
51  #define XEON_PBAR45LMT_OFFSET		0x0008
52  #define XEON_PBAR4LMT_OFFSET		0x0008
53  #define XEON_PBAR5LMT_OFFSET		0x000c
54  #define XEON_PBAR23XLAT_OFFSET		0x0010
55  #define XEON_PBAR45XLAT_OFFSET		0x0018
56  #define XEON_PBAR4XLAT_OFFSET		0x0018
57  #define XEON_PBAR5XLAT_OFFSET		0x001c
58  #define XEON_SBAR23LMT_OFFSET		0x0020
59  #define XEON_SBAR45LMT_OFFSET		0x0028
60  #define XEON_SBAR4LMT_OFFSET		0x0028
61  #define XEON_SBAR5LMT_OFFSET		0x002c
62  #define XEON_SBAR23XLAT_OFFSET		0x0030
63  #define XEON_SBAR45XLAT_OFFSET		0x0038
64  #define XEON_SBAR4XLAT_OFFSET		0x0038
65  #define XEON_SBAR5XLAT_OFFSET		0x003c
66  #define XEON_SBAR0BASE_OFFSET		0x0040
67  #define XEON_SBAR23BASE_OFFSET		0x0048
68  #define XEON_SBAR45BASE_OFFSET		0x0050
69  #define XEON_SBAR4BASE_OFFSET		0x0050
70  #define XEON_SBAR5BASE_OFFSET		0x0054
71  #define XEON_SBDF_OFFSET		0x005c
72  #define XEON_NTBCNTL_OFFSET		0x0058
73  #define XEON_PDOORBELL_OFFSET		0x0060
74  #define XEON_PDBMSK_OFFSET		0x0062
75  #define XEON_SDOORBELL_OFFSET		0x0064
76  #define XEON_SDBMSK_OFFSET		0x0066
77  #define XEON_USMEMMISS_OFFSET		0x0070
78  #define XEON_SPAD_OFFSET		0x0080
79  #define XEON_PBAR23SZ_OFFSET		0x00d0
80  #define XEON_PBAR45SZ_OFFSET		0x00d1
81  #define XEON_PBAR4SZ_OFFSET		0x00d1
82  #define XEON_SBAR23SZ_OFFSET		0x00d2
83  #define XEON_SBAR45SZ_OFFSET		0x00d3
84  #define XEON_SBAR4SZ_OFFSET		0x00d3
85  #define XEON_PPD_OFFSET			0x00d4
86  #define XEON_PBAR5SZ_OFFSET		0x00d5
87  #define XEON_SBAR5SZ_OFFSET		0x00d6
88  #define XEON_WCCNTRL_OFFSET		0x00e0
89  #define XEON_UNCERRSTS_OFFSET		0x014c
90  #define XEON_CORERRSTS_OFFSET		0x0158
91  #define XEON_LINK_STATUS_OFFSET		0x01a2
92  #define XEON_SPCICMD_OFFSET		0x0504
93  #define XEON_DEVCTRL_OFFSET		0x0598
94  #define XEON_DEVSTS_OFFSET		0x059a
95  #define XEON_SLINK_STATUS_OFFSET	0x05a2
96  #define XEON_B2B_SPAD_OFFSET		0x0100
97  #define XEON_B2B_DOORBELL_OFFSET	0x0140
98  #define XEON_B2B_XLAT_OFFSETL		0x0144
99  #define XEON_B2B_XLAT_OFFSETU		0x0148
100  #define XEON_PPD_CONN_MASK		0x03
101  #define XEON_PPD_CONN_TRANSPARENT	0x00
102  #define XEON_PPD_CONN_B2B		0x01
103  #define XEON_PPD_CONN_RP		0x02
104  #define XEON_PPD_DEV_MASK		0x10
105  #define XEON_PPD_DEV_USD		0x00
106  #define XEON_PPD_DEV_DSD		0x10
107  #define XEON_PPD_SPLIT_BAR_MASK		0x40
108  
109  #define XEON_PPD_TOPO_MASK	(XEON_PPD_CONN_MASK | XEON_PPD_DEV_MASK)
110  #define XEON_PPD_TOPO_PRI_USD	(XEON_PPD_CONN_RP | XEON_PPD_DEV_USD)
111  #define XEON_PPD_TOPO_PRI_DSD	(XEON_PPD_CONN_RP | XEON_PPD_DEV_DSD)
112  #define XEON_PPD_TOPO_SEC_USD	(XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_USD)
113  #define XEON_PPD_TOPO_SEC_DSD	(XEON_PPD_CONN_TRANSPARENT | XEON_PPD_DEV_DSD)
114  #define XEON_PPD_TOPO_B2B_USD	(XEON_PPD_CONN_B2B | XEON_PPD_DEV_USD)
115  #define XEON_PPD_TOPO_B2B_DSD	(XEON_PPD_CONN_B2B | XEON_PPD_DEV_DSD)
116  
117  #define XEON_MW_COUNT			2
118  #define HSX_SPLIT_BAR_MW_COUNT		3
119  #define XEON_DB_COUNT			15
120  #define XEON_DB_LINK			15
121  #define XEON_DB_LINK_BIT			BIT_ULL(XEON_DB_LINK)
122  #define XEON_DB_MSIX_VECTOR_COUNT	4
123  #define XEON_DB_MSIX_VECTOR_SHIFT	5
124  #define XEON_DB_TOTAL_SHIFT		16
125  #define XEON_SPAD_COUNT			16
126  
127  /* Use the following addresses for translation between b2b ntb devices in case
128   * the hardware default values are not reliable. */
129  #define XEON_B2B_BAR0_ADDR	0x1000000000000000ull
130  #define XEON_B2B_BAR2_ADDR64	0x2000000000000000ull
131  #define XEON_B2B_BAR4_ADDR64	0x4000000000000000ull
132  #define XEON_B2B_BAR4_ADDR32	0x20000000u
133  #define XEON_B2B_BAR5_ADDR32	0x40000000u
134  
135  /* The peer ntb secondary config space is 32KB fixed size */
136  #define XEON_B2B_MIN_SIZE		0x8000
137  
138  /* flags to indicate hardware errata */
139  #define NTB_HWERR_SDOORBELL_LOCKUP	BIT_ULL(0)
140  #define NTB_HWERR_SB01BASE_LOCKUP	BIT_ULL(1)
141  #define NTB_HWERR_B2BDOORBELL_BIT14	BIT_ULL(2)
142  #define NTB_HWERR_MSIX_VECTOR32_BAD	BIT_ULL(3)
143  #define NTB_HWERR_BAR_ALIGN		BIT_ULL(4)
144  #define NTB_HWERR_LTR_BAD		BIT_ULL(5)
145  
146  extern struct intel_b2b_addr xeon_b2b_usd_addr;
147  extern struct intel_b2b_addr xeon_b2b_dsd_addr;
148  
149  int ndev_init_isr(struct intel_ntb_dev *ndev, int msix_min, int msix_max,
150  		int msix_shift, int total_shift);
151  enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd);
152  void ndev_db_addr(struct intel_ntb_dev *ndev,
153  				phys_addr_t *db_addr, resource_size_t *db_size,
154  				phys_addr_t reg_addr, unsigned long reg);
155  u64 ndev_db_read(struct intel_ntb_dev *ndev, void __iomem *mmio);
156  int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits,
157  				void __iomem *mmio);
158  int ndev_mw_to_bar(struct intel_ntb_dev *ndev, int idx);
159  int intel_ntb_mw_count(struct ntb_dev *ntb, int pidx);
160  int intel_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int idx,
161  		resource_size_t *addr_align, resource_size_t *size_align,
162  		resource_size_t *size_max);
163  int intel_ntb_peer_mw_count(struct ntb_dev *ntb);
164  int intel_ntb_peer_mw_get_addr(struct ntb_dev *ntb, int idx,
165  		phys_addr_t *base, resource_size_t *size);
166  u64 intel_ntb_link_is_up(struct ntb_dev *ntb, enum ntb_speed *speed,
167  		enum ntb_width *width);
168  int intel_ntb_link_disable(struct ntb_dev *ntb);
169  u64 intel_ntb_db_valid_mask(struct ntb_dev *ntb);
170  int intel_ntb_db_vector_count(struct ntb_dev *ntb);
171  u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector);
172  int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits);
173  int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits);
174  int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb);
175  int intel_ntb_spad_count(struct ntb_dev *ntb);
176  u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx);
177  int intel_ntb_spad_write(struct ntb_dev *ntb, int idx, u32 val);
178  u32 intel_ntb_peer_spad_read(struct ntb_dev *ntb, int pidx, int sidx);
179  int intel_ntb_peer_spad_write(struct ntb_dev *ntb, int pidx, int sidx,
180  		u32 val);
181  int intel_ntb_peer_spad_addr(struct ntb_dev *ntb, int pidx, int sidx,
182  				    phys_addr_t *spad_addr);
183  int xeon_link_is_up(struct intel_ntb_dev *ndev);
184  
185  #endif
186