Searched refs:XEHP_L3SQCREG5 (Results 1 – 4 of 4) sorted by relevance
32 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,112 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,131 XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
386 #define XEHP_L3SQCREG5 XE_REG_MCR(0xb158) macro
1006 #define XEHP_L3SQCREG5 MCR_REG(0xb158) macro
682 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, in dg2_ctx_gt_tuning_init()