Searched refs:X1CLK (Results 1 – 8 of 8) sorted by relevance
82 #define X1CLK 0x0 /* x1 clock mode */ macro
802 wr(scc,R4,X1CLK|SDLC); /* *1 clock, SDLC mode */ in init_channel()
135 #define X1CLK 0x0 /* x1 clock mode */ macro
108 #define X1CLK 0x0 /* x1 clock mode */ macro
116 #define X1CLK 0x0 /* x1 clock mode */ macro
196 #define X1CLK 0x0 /* x1 clock mode */ macro
759 write_zsreg(uap, 4, X1CLK | MONSYNC); in pmz_fix_zero_bug_scc()965 uap->curregs[R4] = X1CLK; in pmz_convert_to_zs()
906 zport->regs[4] |= X1CLK; in zs_set_termios()