Searched refs:X16CLK (Results 1 – 9 of 9) sorted by relevance
83 #define X16CLK 0x40 /* x16 clock mode */ macro
136 #define X16CLK 0x40 /* x16 clock mode */ macro
109 #define X16CLK 0x40 /* x16 clock mode */ macro
117 #define X16CLK 0x40 /* x16 clock mode */ macro
197 #define X16CLK 0x40 /* x16 clock mode */ macro
779 write_zsreg(uap, 4, X16CLK | SB_MASK); in pmz_fix_zero_bug_scc()823 uap->curregs[R4] = X16CLK | SB1; in __pmz_startup()974 uap->curregs[R4] = X16CLK; in pmz_convert_to_zs()984 uap->curregs[R4] = X16CLK; in pmz_convert_to_zs()
871 up->curregs[R4] |= X16CLK; in sunzilog_convert_to_zs()1345 up->curregs[R4] = PAR_EVEN | X16CLK | SB1; in sunzilog_init_hw()1361 up->curregs[R4] = PAR_EVEN | X16CLK | SB1; in sunzilog_init_hw()
805 up->curregs[R4] |= X16CLK; in ip22zilog_convert_to_zs()1137 up->curregs[R4] = PAR_EVEN | X16CLK | SB1; in ip22zilog_prepare()
113 X16CLK | SB1, /* write 4 */903 zport->regs[4] |= X16CLK; in zs_set_termios()