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Searched refs:WREG32_ENDPOINT (Results 1 – 4 of 4) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/radeon/
Ddce6_afmt.c150 WREG32_ENDPOINT(dig->pin->offset, in dce6_afmt_write_latency_fields()
175 WREG32_ENDPOINT(dig->pin->offset, in dce6_afmt_hdmi_write_speaker_allocation()
200 WREG32_ENDPOINT(dig->pin->offset, in dce6_afmt_dp_write_speaker_allocation()
255 WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value); in dce6_afmt_write_sad_regs()
266 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, in dce6_audio_enable()
Ddce3_1_afmt.c46 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); in dce3_2_afmt_hdmi_write_speaker_allocation()
64 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); in dce3_2_afmt_dp_write_speaker_allocation()
113 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); in dce3_2_afmt_write_sad_regs()
Devergreen_hdmi.c118 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp); in dce4_afmt_write_latency_fields()
136 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); in dce4_afmt_hdmi_write_speaker_allocation()
154 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp); in dce4_afmt_dp_write_speaker_allocation()
203 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value); in evergreen_hdmi_write_sad_regs()
Dradeon_audio.h34 #define WREG32_ENDPOINT(block, reg, v) \ macro