| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn401/ |
| D | dcn401_fpu.c | 38 clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn401_build_wm_range_table_fpu()
39 clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn401_build_wm_range_table_fpu()
40 …clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_laten… in dcn401_build_wm_range_table_fpu()
41 clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn401_build_wm_range_table_fpu()
42 …clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus… in dcn401_build_wm_range_table_fpu()
43 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn401_build_wm_range_table_fpu()
44 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
45 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn401_build_wm_range_table_fpu()
46 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn401_build_wm_range_table_fpu()
47 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn401_build_wm_range_table_fpu()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 370 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_fpu_update_soc_for_wm_a()
373 …ram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_l… in dcn30_fpu_update_soc_for_wm_a()
374 ….sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter… in dcn30_fpu_update_soc_for_wm_a()
375 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_in… in dcn30_fpu_update_soc_for_wm_a()
417 …ram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_l… in dcn30_fpu_calculate_wm_and_dlg()
591 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us; in dcn30_fpu_calculate_wm_and_dlg()
743 base->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn3_fpu_build_wm_range_table()
744 base->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn3_fpu_build_wm_range_table()
745 base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn3_fpu_build_wm_range_table()
746 …base->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_ex… in dcn3_fpu_build_wm_range_table()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.c | 458 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
459 …oc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; in dcn31_update_soc_for_wm_a()
460 …soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit… in dcn31_update_soc_for_wm_a()
461 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
469 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
474 …oc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us; in dcn315_update_soc_for_wm_a()
476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn315_update_soc_for_wm_a()
478 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn315_update_soc_for_wm_a()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| D | dcn301_fpu.c | 221 .wm_inst = WM_A,
258 .wm_inst = WM_A,
448 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn301_fpu_calculate_wm_and_dlg()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 211 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn32_build_wm_range_table_fpu()
212 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn32_build_wm_range_table_fpu()
213 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_… in dcn32_build_wm_range_table_fpu()
214 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
215 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn32_build_wm_range_table_fpu()
216 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn32_build_wm_range_table_fpu()
217 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
218 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn32_build_wm_range_table_fpu()
219 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn32_build_wm_range_table_fpu()
220 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn32_build_wm_range_table_fpu()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| D | dcn316_clk_mgr.c | 268 .wm_inst = WM_A,
305 .wm_inst = WM_A,
391 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn316_build_watermark_ranges()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 346 .wm_inst = WM_A,
383 .wm_inst = WM_A,
469 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn31_build_watermark_ranges()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| D | dcn315_clk_mgr.c | 306 .wm_inst = WM_A,
343 .wm_inst = WM_A,
429 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn315_build_watermark_ranges()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| D | dcn401_clk_mgr.c | 181 clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn401_build_wm_range_table()
182 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn401_build_wm_range_table()
183 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn401_build_wm_range_table()
184 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn401_build_wm_range_table()
185 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz; in dcn401_build_wm_range_table()
186 clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF; in dcn401_build_wm_range_table()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr.h | 34 #define WM_A 0 macro
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_clk_mgr.c | 406 .wm_inst = WM_A,
443 .wm_inst = WM_A,
534 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn314_build_watermark_ranges()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 771 .wm_inst = WM_A,
808 .wm_inst = WM_A,
845 .wm_inst = WM_A,
882 .wm_inst = WM_A,
919 .wm_inst = WM_A,
956 .wm_inst = WM_A,
2315 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn21_calculate_wm()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| D | dcn_calcs.c | 43 #define WM_A 0 macro
1524 ranges.reader_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1529 ranges.writer_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1536 ranges.reader_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
1541 ranges.writer_wm_sets[0].wm_inst = WM_A; in dcn_bw_notify_pplib_of_wm_ranges()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| D | dcn35_clk_mgr.c | 545 .wm_inst = WM_A,
582 .wm_inst = WM_A,
690 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in dcn35_build_watermark_ranges()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 504 ranges->writer_wm_sets[0].wm_inst = WM_A; in build_watermark_ranges()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.c | 434 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; in vg_build_watermark_ranges()
|