Searched refs:VPU_40XX_HOST_SS_AON_PWR_ISO_EN0 (Results 1 – 2 of 2) sorted by relevance
104 #define VPU_40XX_HOST_SS_AON_PWR_ISO_EN0 0x00030020u macro
384 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0); in pwr_island_isolation_drive_40xx()387 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val); in pwr_island_isolation_drive_40xx()389 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, CSS_CPU, val); in pwr_island_isolation_drive_40xx()391 REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISO_EN0, val); in pwr_island_isolation_drive_40xx()