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Searched refs:VPU_40XX_HOST_IF_TBU_MMUSSIDV (Results 1 – 2 of 2) sorted by relevance

/linux-6.12.1/drivers/accel/ivpu/
Divpu_hw_ip.c780 u32 val = REGV_RD32(VPU_40XX_HOST_IF_TBU_MMUSSIDV); in ivpu_hw_ip_tbu_mmu_enable_40xx()
782 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
783 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU0_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
784 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
785 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU1_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
786 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_AWMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
787 val = REG_SET_FLD(VPU_40XX_HOST_IF_TBU_MMUSSIDV, TBU2_ARMMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
789 REGV_WR32(VPU_40XX_HOST_IF_TBU_MMUSSIDV, val); in ivpu_hw_ip_tbu_mmu_enable_40xx()
Divpu_hw_40xx_reg.h151 #define VPU_40XX_HOST_IF_TBU_MMUSSIDV 0x00360004u macro