Searched refs:VPU_37XX_HOST_SS_AON_PWR_ISO_EN0 (Results 1 – 2 of 2) sorted by relevance
95 #define VPU_37XX_HOST_SS_AON_PWR_ISO_EN0 0x00030020u macro
372 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0); in pwr_island_isolation_drive_37xx()375 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); in pwr_island_isolation_drive_37xx()377 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, MSS_CPU, val); in pwr_island_isolation_drive_37xx()379 REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0, val); in pwr_island_isolation_drive_37xx()