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Searched refs:VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_1_sh_mask.h18529 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000 macro
Dgfx_8_0_sh_mask.h17939 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h17565 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro
Dgc_9_1_sh_mask.h18872 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro
Dgc_9_4_3_sh_mask.h20891 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro
Dgc_9_2_1_sh_mask.h18763 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro
Dgc_9_4_2_sh_mask.h11008 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro
Dgc_11_5_0_sh_mask.h18573 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro
Dgc_11_0_0_sh_mask.h22595 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro
Dgc_12_0_0_sh_mask.h13824 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro
Dgc_11_0_3_sh_mask.h24937 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro
Dgc_10_1_0_sh_mask.h25102 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro
Dgc_10_3_0_sh_mask.h23299 #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK … macro