Home
last modified time | relevance | path

Searched refs:V3D_CORE_WRITE (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/v3d/ !
Dv3d_gem.c29 V3D_CORE_WRITE(core, V3D_CTL_MISCCFG, V3D_MISCCFG_OVRTMUOUT); in v3d_init_core()
34 V3D_CORE_WRITE(core, V3D_CTL_L2TFLSTA, 0); in v3d_init_core()
35 V3D_CORE_WRITE(core, V3D_CTL_L2TFLEND, ~0); in v3d_init_core()
48 V3D_CORE_WRITE(core, V3D_GMP_CFG(v3d->ver), V3D_GMP_CFG_STOP_REQ); in v3d_idle_axi()
157 V3D_CORE_WRITE(core, V3D_CTL_L2CACTL, in v3d_invalidate_l2c()
174 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, in v3d_flush_l2t()
196 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF); in v3d_clean_caches()
203 V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, in v3d_clean_caches()
221 V3D_CORE_WRITE(core, V3D_CTL_SLCACTL, in v3d_invalidate_slices()
Dv3d_irq.c73 V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << V3D_MMU_PAGE_SHIFT); in v3d_overflow_mem_work()
74 V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size); in v3d_overflow_mem_work()
90 V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts); in v3d_irq()
225 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver)); in v3d_irq_init()
270 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS(v3d->ver)); in v3d_irq_enable()
271 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS(v3d->ver)); in v3d_irq_enable()
285 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0); in v3d_irq_disable()
290 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver)); in v3d_irq_disable()
Dv3d_debugfs.c239 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3, in v3d_measure_clock()
242 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1); in v3d_measure_clock()
243 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1); in v3d_measure_clock()
245 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0, in v3d_measure_clock()
247 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1); in v3d_measure_clock()
248 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN, in v3d_measure_clock()
Dv3d_perfmon.c254 V3D_CORE_WRITE(0, V3D_V4_PCTR_0_SRC_X(source), channel); in v3d_perfmon_start()
257 V3D_CORE_WRITE(0, V3D_V4_PCTR_0_CLR, mask); in v3d_perfmon_start()
258 V3D_CORE_WRITE(0, V3D_PCTR_0_OVERFLOW, mask); in v3d_perfmon_start()
259 V3D_CORE_WRITE(0, V3D_V4_PCTR_0_EN, mask); in v3d_perfmon_start()
282 V3D_CORE_WRITE(0, V3D_V4_PCTR_0_EN, 0); in v3d_perfmon_stop()
Dv3d_sched.c196 V3D_CORE_WRITE(0, V3D_PTB_BPOS, 0); in v3d_bin_job_run()
219 V3D_CORE_WRITE(0, V3D_CLE_CT0QMA, job->qma); in v3d_bin_job_run()
220 V3D_CORE_WRITE(0, V3D_CLE_CT0QMS, job->qms); in v3d_bin_job_run()
223 V3D_CORE_WRITE(0, V3D_CLE_CT0QTS, in v3d_bin_job_run()
227 V3D_CORE_WRITE(0, V3D_CLE_CT0QBA, job->start); in v3d_bin_job_run()
228 V3D_CORE_WRITE(0, V3D_CLE_CT0QEA, job->end); in v3d_bin_job_run()
272 V3D_CORE_WRITE(0, V3D_CLE_CT1QBA, job->start); in v3d_render_job_run()
273 V3D_CORE_WRITE(0, V3D_CLE_CT1QEA, job->end); in v3d_render_job_run()
347 V3D_CORE_WRITE(0, csd_cfg0_reg + 4 * i, job->args.cfg[i]); in v3d_csd_job_run()
355 V3D_CORE_WRITE(0, V3D_V7_CSD_QUEUED_CFG7, 0); in v3d_csd_job_run()
[all …]
Dv3d_drv.h256 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) macro