| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v5_0_0.c | 683 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v5_0_0_start_dpg_mode()
706 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v5_0_0_start_dpg_mode()
789 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v5_0_0_start()
996 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v5_0_0_stop()
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| D | vcn_v4_0_5.c | 897 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v4_0_5_start_dpg_mode()
944 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v4_0_5_start_dpg_mode()
1031 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v4_0_5_start()
1262 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v4_0_5_stop()
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| D | vcn_v4_0_3.c | 794 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v4_0_3_start_dpg_mode()
843 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v4_0_3_start_dpg_mode()
1116 UVD_VCPU_CNTL__CLK_EN_MASK, in vcn_v4_0_3_start()
1117 ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v4_0_3_start()
1352 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v4_0_3_stop()
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| D | vcn_v4_0.c | 982 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v4_0_start_dpg_mode()
1029 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v4_0_start_dpg_mode()
1119 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v4_0_start()
1599 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v4_0_stop()
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| D | vcn_v2_5.c | 890 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v2_5_start_dpg_mode()
953 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v2_5_start_dpg_mode()
1048 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v2_5_start()
1477 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v2_5_stop()
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| D | vcn_v3_0.c | 1010 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v3_0_start_dpg_mode()
1071 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v3_0_start_dpg_mode()
1170 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v3_0_start()
1617 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v3_0_stop()
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| D | vcn_v2_0.c | 861 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v2_0_start_dpg_mode()
999 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v2_0_start()
1215 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); in vcn_v2_0_stop()
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| D | vcn_v1_0.c | 895 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v1_0_start_spg_mode()
1026 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; in vcn_v1_0_start_dpg_mode()
1184 ~UVD_VCPU_CNTL__CLK_EN_MASK); in vcn_v1_0_stop_spg_mode()
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| D | uvd_v7_0.c | 905 UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v7_0_sriov_start()
1036 UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v7_0_start()
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| D | uvd_v6_0.c | 794 WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); in uvd_v6_0_start()
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_7_0_sh_mask.h | 665 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
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| D | uvd_3_1_sh_mask.h | 543 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
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| D | uvd_4_0_sh_mask.h | 766 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L macro
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| D | uvd_4_2_sh_mask.h | 547 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
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| D | uvd_5_0_sh_mask.h | 579 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
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| D | uvd_6_0_sh_mask.h | 581 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 macro
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_sh_mask.h | 1187 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
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| D | vcn_2_5_sh_mask.h | 2759 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
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| D | vcn_2_0_0_sh_mask.h | 2759 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
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| D | vcn_2_6_0_sh_mask.h | 112 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
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| D | vcn_3_0_0_sh_mask.h | 3818 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
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| D | vcn_5_0_0_sh_mask.h | 3767 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
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| D | vcn_4_0_5_sh_mask.h | 3933 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
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| D | vcn_4_0_0_sh_mask.h | 4066 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
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| D | vcn_4_0_3_sh_mask.h | 4104 #define UVD_VCPU_CNTL__CLK_EN_MASK … macro
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