Home
last modified time | relevance | path

Searched refs:UVD_SUVD_CGC_GATE__IME_HEVC_MASK (Results 1 – 16 of 16) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h478 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK macro
Dvcn_2_5_sh_mask.h2107 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK macro
Dvcn_2_0_0_sh_mask.h3233 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK macro
Dvcn_2_6_0_sh_mask.h3778 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK macro
Dvcn_3_0_0_sh_mask.h2843 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK macro
Dvcn_5_0_0_sh_mask.h1165 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK macro
Dvcn_4_0_5_sh_mask.h1356 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK macro
Dvcn_4_0_0_sh_mask.h1360 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK macro
Dvcn_4_0_3_sh_mask.h1360 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK macro
/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0_5.c731 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); in vcn_v4_0_5_disable_clock_gating()
Dvcn_v4_0_3.c635 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); in vcn_v4_0_3_disable_clock_gating()
Dvcn_v1_0.c594 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); in vcn_v1_0_disable_clock_gating()
Dvcn_v2_0.c622 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); in vcn_v2_0_disable_clock_gating()
Dvcn_v4_0.c795 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); in vcn_v4_0_disable_clock_gating()
Dvcn_v2_5.c712 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); in vcn_v2_5_disable_clock_gating()
Dvcn_v3_0.c830 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK in vcn_v3_0_disable_clock_gating()