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Searched refs:UVD_POWER_STATUS__UVD_POWER_STATUS_MASK (Results 1 – 23 of 23) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0_5.c610 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; in vcn_v4_0_5_enable_static_power_gating()
881 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_5_start_dpg_mode()
1188 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_5_stop_dpg_mode()
1195 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_5_stop_dpg_mode()
1312 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_5_pause_dpg_mode()
1326 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_5_pause_dpg_mode()
1638 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v4_0_5_print_ip_state()
1670 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v4_0_5_dump_ip_state()
Dvcn_v2_5.c875 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_start_dpg_mode()
1030 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_start()
1406 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_stop_dpg_mode()
1419 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_stop_dpg_mode()
1486 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, in vcn_v2_5_stop()
1487 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_stop()
1512 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_pause_dpg_mode()
1557 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_pause_dpg_mode()
1563 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_5_pause_dpg_mode()
1948 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v2_5_print_ip_state()
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Dvcn_v1_0.c789 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; in vcn_1_0_enable_static_power_gating()
1214 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v1_0_stop_dpg_mode()
1231 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v1_0_stop_dpg_mode()
1276 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v1_0_pause_dpg_mode()
1306 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v1_0_pause_dpg_mode()
1332 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v1_0_pause_dpg_mode()
1367 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v1_0_pause_dpg_mode()
1947 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v1_0_print_ip_state()
1979 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v1_0_dump_ip_state()
Dvcn_v5_0_0.c578 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; in vcn_v5_0_0_enable_static_power_gating()
670 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v5_0_0_start_dpg_mode()
923 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v5_0_0_stop_dpg_mode()
1043 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v5_0_0_pause_dpg_mode()
1365 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v5_0_print_ip_state()
1397 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v5_0_dump_ip_state()
Dvcn_v4_0.c661 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; in vcn_v4_0_enable_static_power_gating()
967 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_start_dpg_mode()
1525 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_stop_dpg_mode()
1532 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_stop_dpg_mode()
1649 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_pause_dpg_mode()
1662 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_pause_dpg_mode()
2180 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v4_0_print_ip_state()
2212 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v4_0_dump_ip_state()
Dvcn_v3_0.c697 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; in vcn_v3_0_enable_static_power_gating()
995 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v3_0_start_dpg_mode()
1546 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v3_0_stop_dpg_mode()
1559 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v3_0_stop_dpg_mode()
1660 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v3_0_pause_dpg_mode()
1711 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v3_0_pause_dpg_mode()
2274 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v3_0_print_ip_state()
2306 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v3_0_dump_ip_state()
Dvcn_v2_0.c807 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; in vcn_v2_0_enable_static_power_gating()
1155 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_0_stop_dpg_mode()
1168 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_0_stop_dpg_mode()
1261 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_0_pause_dpg_mode()
1309 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v2_0_pause_dpg_mode()
2056 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v2_0_print_ip_state()
2088 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v2_0_dump_ip_state()
Dvcn_v4_0_3.c772 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_3_start_dpg_mode()
1275 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_3_stop_dpg_mode()
1282 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); in vcn_v4_0_3_stop_dpg_mode()
1755 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v4_0_3_print_ip_state()
1788 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; in vcn_v4_0_3_dump_ip_state()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h36 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK macro
Duvd_3_1_sh_mask.h737 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1 macro
Duvd_4_0_sh_mask.h584 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000001L macro
Duvd_4_2_sh_mask.h743 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1 macro
Duvd_5_0_sh_mask.h927 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3 macro
Duvd_6_0_sh_mask.h915 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3 macro
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h80 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK macro
Dvcn_2_5_sh_mask.h1520 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK macro
Dvcn_2_0_0_sh_mask.h1517 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK macro
Dvcn_2_6_0_sh_mask.h2958 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK macro
Dvcn_3_0_0_sh_mask.h2054 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK macro
Dvcn_5_0_0_sh_mask.h5351 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK macro
Dvcn_4_0_5_sh_mask.h6174 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK macro
Dvcn_4_0_0_sh_mask.h6347 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK macro
Dvcn_4_0_3_sh_mask.h7151 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK macro