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Searched refs:UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK (Results 1 – 11 of 11) sorted by relevance

/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/
Djpeg_v3_0.c272 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); in jpeg_v3_0_disable_static_power_gating()
307 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); in jpeg_v3_0_enable_static_power_gating()
Djpeg_v4_0.c311 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); in jpeg_v4_0_disable_static_power_gating()
346 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); in jpeg_v4_0_enable_static_power_gating()
Djpeg_v2_0.c215 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); in jpeg_v2_0_disable_power_gating()
246 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); in jpeg_v2_0_enable_power_gating()
Djpeg_v4_0_3.c493 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); in jpeg_v4_0_3_start()
592 UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); in jpeg_v4_0_3_stop()
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_5_sh_mask.h1511 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK macro
Dvcn_2_0_0_sh_mask.h1508 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK macro
Dvcn_2_6_0_sh_mask.h2949 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK macro
Dvcn_3_0_0_sh_mask.h2042 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK macro
Dvcn_4_0_5_sh_mask.h6162 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK macro
Dvcn_4_0_0_sh_mask.h6335 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK macro
Dvcn_4_0_3_sh_mask.h7139 #define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK macro